English/Japanese

Yasuhiro TAKAHASHI






Yasuhiro TAKAHASHI was born in Yamagata, Japan, in July, 1977. He received a B.E., M.E., and Ph.D. in electronic engineering from Yamagata University, Japan in 2000, 2002, and 2005, respectively. He was a research associate at the Department of Electrical and Electronic Engineering, Faculty of Engineering, Gifu University, from April 2005 to March 2007. He was an assistant professor there from April 2007 to November 2014 and is currently an associate professor.

His research interests include low-power VLSI design, with a particular emphasis on analog/digital circuits, CAD techniques for implementing high-performance DSP functions, and a new approach to nonlinear circuits design using memristors. He has published 170+ papers in refereed journals and conference papers in these and related areas.

He received an IEICE 2017 system and signal processing subsociety achievement award, IEEE IMPACT-EMAP 2014 best poster award, a 9th LSI IP design award in 2007, and also received a 2002 master's degree thesis award of the Graduate School of Science and Engineering, Yamagata University.

He holds 13 (One U.S., 11 Japan, and One China) patents regarding low-power circuit design using adiabatic switching principle.

He is a member of IEEE, IEEJ, and IEICE.


To contant him:
Address: Dept. of Electr., Electro. and Comput. Eng., Gifu Univ., 1-1 Yanagido, Gifu-shi, 501-1193, Japan
Phone & Fax: +81-58-293-2692
Email: yasut at gifu-u.ac.jp
Room no. : A307 (at Engineering Building)
Facebook Unique URL: yasut.takahashi
ResearchGate: https://www.researchgate.net/profile/Yasuhiro-Takahashi-3
Linkedin: https://jp.linkedin.com/pub/yasuhiro-takahashi/55/b24/439/en
Researchmap: https://researchmap.jp/yasut_gifuuniv/

[Journal paper]

  1. T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "A 16-channel optical receiver circuit for multi-core fiber based co-packaged optics module in a 65-nm CMOS chip," IEEE Trans. Circuits and Syst.-II, vol. 71, no. 5, 2024 (Accepted). (Link to DOI).

  2. T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks," Microelectronics Journal, vol. 145, 106120 (10 pages), 2024. (Link to DOI).

  3. Y. Takahashi, D. Ito, M. Nakamura, A. Tsuchiya, T. Inoue, and K. Kishine, "Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process," IEICE Electronics Express, vol. 20, no. 18, 20230339 (6 pages), 2023. (Link to DOI).

  4. D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya, and K. Kishine, "10 Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks," IEICE Electronics Express, vol. 20, no. 14, 20230238 (6 pages), 2023. (Link to DOI).

  5. Y. Takahashi, D. Ito, M. Nakamura, A. Tsuchiya, T. Inoue, and K. Kishine, "Low-power regulated cascode CMOS transimpedance amplifier with local feedback circuit," MDPI Electronics, vol. 11, no. 6, 854 (11 pages), March 2022. (Link to DOI).

  6. C. Monteiro, and Y. Takahashi, "Ultra-low-power FinFETs-based TPCA-PUF circuit for secure IoT devices," MDPI Sensors, vol. 21, no. 24, 8302 (13 pages), Dec. 2021. (Link to DOI).

  7. C. Monteiro, and Y. Takahashi, "Low-power two-phase clocking adiabatic PUF circuit," MDPI Electronics, vol. 10, no. 11, 1258 (15 pages), June 2021. (Link to DOI).

  8. Y. Takahashi, H. Koyasu, S.D. Kumar, and H. Thapliyal, "Quasi-adiabatic SRAM based slicon physical unclonable function," Springer Nature Computer Science, vol. 1, no. 5, 237 (7 pages), Sept. 2020. (Link to DOI).

  9. H. Koyasu, and Y. Takahashi, "Performance and security evaluation of S-box using current-pass optimized symmetric pass gate adiabatic logic," Springer Nature Computer Science, vol. 1, no. 4, 199 (9 pages), July 2020. (Link to DOI).

  10. Y. Masaki, and Y. Takahashi, "Evaluation of adiabatic S-box with diode connected transistors as countermeasure against correlation power analysis attacks," IEEJ Trans. Electronics, Information and Systems, vol. 140, no. 2, pp. 187-193, Feb. 2020 (Japanese Edition). (Link to DOI).

  11. X. Chen, and Y. Takahashi, "Floating active inductor based trans-impedance amplifier in 0.18 µm CMOS technology for optical applications," MDPI Electronics, vol. 8, no. 12, 1547 (12 pages), Dec. 2019. (Link to DOI).

  12. M. Han, Y. Takahashi, and T. Sekine, "Non-floating and low-power adiabatic logic circuit," IEICE Electronics Express, vol. 16, no. 17, 20190400 (6 pages), 2019. (Link to DOI).

  13. R. Wakemoto, Y. Takahashi, and T. Sekine, "FinFET 4T-SRAM operable at near-threshold region," Electronics and Communications in Japan, vol. 102, no. 5, pp. 19-26, May 2019 (Translated from IEEJ Trans. Electronics, Information and Systems, vol. 139, no. 1, pp. 43-49, Jan. 2019). (Link to DOI).

  14. H. Koyasu, and Y. Takahashi, "Current pass optimized symmetric pass gate adiabatic logic for cryptographic circuits," IPSJ Trans. System LSI Design Methodology, vol. 12, pp. 50-52, Feb. 2019. (Link to DOI).

  15. R. Wakemoto, Y. Takahashi, and T. Sekine, "FinFET 4T-SRAM operable at near-threshold region," IEEJ Trans. Electronics, Information and Systems, vol. 139, no. 1, pp. 43-49, Jan. 2019 (Japanese Edition). (Link to DOI).

  16. Y. Takahashi, T. Sekine, and M. Yokoyama, "Memristor-based pseudo-random pattern generator using relaxation oscillator," IEEJ Trans. Electrical and Electronic Engineering, vol. 12, no. 6, pp. 963-964, Nov. 2017. (Link to DOI).

  17. K. Kato, Y. Takahashi, and T. Sekine, "Two phase clocked subthreshold adiabatic logic circuit," IEICE Electronics Express, vol. 12, no. 20, 20150695 (12 pages), 2015. (Link to DOI).

  18. C. Monteiro, Y. Takahashi, and T. Sekine, "Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design," IET Circuits, Devices & Systems, vol. 9, no. 5, pp. 362-269, Sept. 2015. (Link to DOI).

  19. Y. Takahashi, and H. Sato, "Low-power supply circuit using off-chip resonant circuit for adiabatic logic," Electronics and Communications in Japan, vol. 98, no. 3, pp. 1-8, March, 2015 (Translated from IEEJ Trans. Electronics, Information and Systems, vol. 133, no. 2, pp. 250-255, Feb. 2013). (Link to DOI).

  20. Y. Takahashi, T. Sekine, and M. Yokoyama, "SPICE model of memristive device using Tukey window function," IEICE Electronics Express, vol. 12, no. 5, 20150149 (7 pages), 2015. (Link to DOI).

  21. Y. Takahashi, N. A. Nayan, T. Sekine, and M. Yokoyama, "Low power adiabatic 9T static random access memory," IET J. Engineering, 6 pages, June 2014. (Link to DOI).

  22. N. Maeda, S. Fukai, T. Naoi, K. Ichikawa, T. Sekine, and Y. Takahashi, "S parameter estimation of n port reciprocal circuits with n-1 port measurements," IEICE Trans. Electron., vol. J96-C, pp. 436-470, Dec. 2013 (Japanese Edition). (Link to IEICE SEARCH).

  23. C. Monteiro, Y. Takahashi, and T. Sekine, "Low power bit-parallel cellular multiplier implementation in secure dual-rail adiabatic logic," IACSIT International J. Modeling and Optimization, vol. 3, no. 4, pp. 329-332, Aug. 2013. (PDF File: 1040kB, MD5: 21acf0043a8f9d5950d58a9c5d9bba49)

  24. C. Monteiro, Y. Takahashi, and T. Sekine, "Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level," Microelectronics Journal, vol. 44, no. 6, pp. 496-503, June 2013. (PDF File: 1080kB, MD5: 50235b0f64f3cb6701cd655f80377f9a)

  25. Y. Takahashi, and H. Sato, "Low power supply circuit using off-chip resonant circuit for adiabatic logic," IEEJ Trans. Electronics, Information and Systems, vol. 133, no. 2, pp. 250-255, Feb. 2013 (Japanese Edition). (Link to DOI).

  26. N. A. Nayan, Y. Takahashi, and T. Sekine, "The ramped-step voltage in adiabatic logic circuits: analysis of parameters to further reduce power dissipation," Research J. of Applied Sciences, Engineering and Technology, vol. 5, no. 1, pp. 114-117, Jan. 2013. (PDF File: 198kB, MD5: 6641909a7fac30e7c1d2903d17f403ca)

  27. N. A. Nayan, Y. Takahashi, and T. Sekine, "LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier," Microelectronics Journal, vol. 43, no. 4, pp. 244-249, April 2012. (PDF File: 1066kB, MD5: 12449d1c414163ed85b56ce09ffe4c74)

  28. N. A. Nayan, Y. Takahashi, and T. Sekine, "Low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier," Far East J. Electronics and Communications, vol. 5, no. 1, pp. 1-13, Sept. 2010. (PDF File: 2807kB, MD5: 473c9b7e73ff2bb65ccd930e9df253c6)

  29. N. A. Nayan, Y. Takahashi, and T. Sekine, "Two phase clocked adiabatic static CMOS logic and its logic family," IEEK J. Semiconductor Technology and Science, vol. 10 no. 1, pp. 1-10, March 2010. (PDF File: 732kB, MD5: 36d8bd9f08527b4757df8392a8490fa2)

  30. Y. Takahashi, T. Sekine, and M. Yokoyama, "Two-phase clocked CMOS adiabatic logic," Far East J. Electronics and Communications, vol. 3, no. 1, pp. 17-34, April 2009. (PDF File: 213kB, MD5: 53bb49e1e26f4d154f290ccfebce8ca1)

  31. Y. Takahashi, T. Sekine, and M. Yokoyama, "Design of a 16-bit non-pipelined RISC CPU in a two phase drive adiabatic dynamic CMOS logic," IACSIT International J. Computer and Electrical Engineering, vol. 1, no. 1, pp. 71-76, April 2009. (PDF File: 375kB, MD5: cacc3035d8bd40a518cc75f21b6183c0)

  32. Y. Takahashi, T. Sekine, and M. Yokoyama, "VLSI implementation of a 4×4-bit multiplier in a two phase drive adiabatic dynamic CMOS logic," IEICE Trans. Electron., vol. E90-C, no. 10, pp. 2002-2006, Oct. 2007. (PDF File: 431kB, MD5: 2b72bd6be4716f810f6e33d92b8cc555)

  33. Y. Takahashi, T. Sekine, and M. Yokoyama, "A 70 MHz multiplierless FIR Hilbert transformer in 0.35 µm standard CMOS library," IEICE Trans. Fundamentals, vol. E90-A, no. 7, pp. 1376-1383, July 2007. (PDF File: 731kB, MD5: f6ad23b44824ea7f0e7a6f1fd92cac60)

  34. Y. Takahashi, K. Konta, K. Takahashi, M. Yokoyama, K. Shouno, and M. Mizunuma, "Carry propagation free adder/subtracter VLSI using adiabatic dynamic CMOS logic circuit technology," IEICE Trans. Fundamentals, vol. E86-A, no. 6, pp. 1437-1444, June 2003. (PDF File: 562kB, MD5: 7c51886e80d23e8f231921bf1f9d7b94)

[International conference paper]

  1. T. Inoue, A. Tsuchiya, K. Kishine, Y. Takahashi, D. Ito, and M. Nakamura, "A 16-channel optical receiver circuit for a multicore fiber-based co-packaged optics module in a 65-nm CMOS chip," Proc. IEEE ISCAS 2024, May 19-22, Singapore (Accepted).

  2. Y. Takahashi, and K. Tominaga, "A 0.06 mm2, 0.9 pJ/bit, 25 Gb/s optical receiver front-end module in 65 nm CMOS," Proc. IEEE ICCCAS 2024, May 10-12, Xiamen, China (Accepted).

  3. K. Tominaga, and Y. Takahashi, "Low-power, 25-Gb/s active voltage current feedback transimpedance amplifier in 65-nm CMOS," Proc. IEEE ICEIC 2024, pp. 120-123, Jan 28-31, Taipei, Taiwan.

  4. Y. Takahashi, D. Ito, M. Nakamura, A. Tsuchiya, T. Inoue, and K. Kishine, "A 25-Gb/s active feedback transimpedance amplifier in 65-nm CMOS," Proc. IEEE ICEIC 2024, pp. 185-188, Jan 28-31, Taipei, Taiwan.

  5. T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "A 4×32-Gb/s VCSEL driver with adaptive feedforward equalization in 65-nm CMOS," Proc. IEEE ICECS 2023, Dec. 4-7, Istanbul, Turkey.

  6. D. Ito, Y. Takahashi, and M. Nakamura, T. Inoue, A. Tsuchiya, K. Kishine, "4-ch 25-Gb/s small and low-power VCSEL driver circuit with unbalanced CML in 65-nm CMOS," Proc. IEEE ISOCC 2023, pp. 13-14, Oct. 25-28, Jeju, Korea.

  7. A. Tsuchiya, T. Inoue, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "High-speed, low-power, and small-area optical receiver in 65-nm CMOS," Proc. IEEE ASICON 2023, Oct. 24-27, Nanjing, China (Invited Paper).

  8. D. Ito, Y. Takahashi, and M. Nakamura, T. Inoue, A. Tsuchiya, K. Kishine, "Burst-mode driver circuit with on-chip bias tee for in-Vehicle optical networks," Proc. IEEJ AVIC 2022, pp. 55-59, Oct. 31-Nov. 2, Hiroshima, Japan.

  9. T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "A burst-mode TIA with automatic power saving and DC wander reduction in 65-nm CMOS," Proc. IEEE ICECS 2022, Oct. 24-26, Glasgrow, UK (Place virtually).

  10. A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito, and M. Nakamura, "A small-area integration of optical receiver using multi-layer inductors and capacitor-under-pad," Proc. IEEE MWSCAS 2022, Aug. 7-10, Fukuoka, Japan (Place virtually).

  11. T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "A 28-Gb/s VCSEL driver with variable output impedance in 65-nm CMOS," Proc. IEEE MWSCAS 2022, Aug. 7-10, Fukuoka, Japan (Place virtually).

  12. A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito, and M. Nakamura, "Capacitor under pad for small area integration of high-speed signal-to-differential amplifier," Proc. IEEE ICEIC 2022, Feb. 6-9, Jeju, Korea (Place virtually).

  13. T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "A burst-mode TIA with adaptive response and stable operation for in-vehicle optical networks," Proc. IEEE ICECS 2021, 6 pages, Nov. 28-Dec. 1, Dubai, UAE (Place virtually).

  14. K. Fukuta, Y. Takahashi, D. Ito, M. Nakamura, T. Jyo, M. Nagatani, Y. Shiratori, M. Mutoh, and H. Nosaka, "49.4-dBΩ 46.8-GHz multiple shunt-shunt feedback regulated cascode TIA in 0.25-µm InP-HBT process," Proc. IEEE APMC 2020, pp. 477-479, Dec. 8-11, Hong Kong (Place virtually).

  15. K. Ogura, and Y. Takahashi, "Special Session: An adiabatic logic based silicon physical unclonable function," Proc. IEEE ICCD 2020, Special Session, 4 pages, Oct. 18-21, Hartford, CT (Place virtually).

  16. X. Chen, and Y. Takahashi,"Design of 10 GHz CMOS optoelectronic receiver analog front-end in low-cost 0.18 µm CMOS technology," Proc. IEEE ISPACS 2019, Session Analog Circuits and Their Applications, 2 pages, Dec. 3-6, Beitou, Taiwan.

  17. R. Ohashi, and Y. Takahashi, "Cryptographic adiabatic logic circuit with bootstrap structure," Proc. IEEJ AVIC 2019, 5 pages, Oct. 28-30, Yilan, Taiwan.

  18. H. Koyasu, and Y. Takahashi, "Proposal and evaluation of low power AES circuit using adiabatic logic," Proc. IEEJ AVIC 2019, 5 pages, Oct. 28-30, Yilan, Taiwan.

  19. T. Fukuura, and Y. Takahashi, "Shunt-series peaking transimpedance amplifier using active inductor with RGC configuration," Proc. IEEJ AVIC 2019, 4 pages, Oct. 28-30, Yilan, Taiwan.

  20. R. Tagawa, and Y. Takahashi, "5.0 GHz, 54.7 dBΩ transimpedance amplifier with negative impedance converter," Proc. IEEJ AVIC 2019, 5 pages, Oct. 28-30, Yilan, Taiwan.

  21. N. Maeda, S. Fukai, T. Sekine, and Y. Takahashi, "Indirect measurement method for S-parameters with measuring a minor number of ports," Proc. IEEE EMC/SIPI 2019, pp. 223-228, July 22-26, New Orleans, LA.

  22. T. Sekine, and Y. Takahashi, "A new S-parameter measurement method with simultaneous calibration and measurement," Proc. IEEE EMC/SIPI 2019, Poster session, July 22-26, New Orleans, LA.

  23. X. Chen, and Y. Takahashi, "Design of a CMOS broadband transimpedance amplifier with floating active inductor," Proc. IEEE ISVLSI 2019, pp. 230-234, July 15-17, Miami, FL.

  24. H. Koyasu, and Y. Takahashi, "Evaluation of power analysis attacks on cryptographic circuit using adiabatic logic," Proc. IEEE ISVLSI 2019, pp. 409-412, July 15-17, Miami, FL.

  25. Y. Takahashi, H. Koyasu, S.D. Kumar, and H. Thapliyal, "Post-layout simulation of quasi-adiabatic logic based physical unclonable function," Proc. IEEE ISVLSI 2019, pp. 443-446, July 15-17, Miami, FL.

  26. T. Sekine, and Y. Takahashi, "An Indirect S-parameters Measurement Method of Chips in a Multi-chip Module through External Terminals," Proc. PIERS 2019, June 17-20, Roma, Itary.

  27. T. Sekine, Y. Takahashi, N. Maeda, S. Fukui, Y. Ishikawa, and K. Oyama, "Estimation of S-parameters of chips in a multi-chip module by indirect measurement through external terminals," Proc. IEICE EMC Sapporo & APEMC 2019, ThuPM2B.1, June 3-7, Sapporo, Japan.

  28. C. Monteiro, A. Maria, and Y. Takahashi, "Low power source biased semi-adiabatic logic circuit for IoT devices," Proc. IEEE ISPACS 2018, pp. 43-47, Nov. 27-30, Okinawa, Japan.

  29. R. Ohashi, and Y. Takahashi, "A new adiabatic logic without charge sharing gate for cryptographic devices," Proc. IEEE ISPACS 2018, pp. 117-121, Nov. 27-30, Okinawa, Japan.

  30. H. Koyasu, and Y. Takahashi, "Current pass optimized-symmetric pass gate adiabatic logic in countermeasures against power analysis attacks," Proc. IEEE ISPACS 2018, pp. 122-126, Nov. 27-30, Okinawa, Japan.

  31. T. Fukuura, and Y. Takahashi, "5.6 GHz, 61.7 dBΩ transimpedance amplifier using active inductor in shunt and series peaking," Proc. IEEE ISPACS 2018, pp. 392-395, Nov. 27-30, Okinawa, Japan.

  32. R. Tagawa, and Y. Takahashi, "5.3 GHz, 69.6 dBΩ transimpedance amplifier with negative impedance converter," Proc. IEEE ISPACS 2018, pp. 396-400, Nov. 27-30, Okinawa, Japan.

  33. B. Da Costa, and Y. Takahashi, "8 GHz trans-impedance amplifier using floating active inductor," Proc. IEEJ AVIC 2018, pp. 53-56, Oct. 31-Nov. 2, Chiang Mai, Thailand.

  34. X. Chen, and Y. Takahashi, "Design and analysis of a 10 GHz trans-impedance amplifier using active inductor in 0.18 µm CMOS process technology," Proc. IEEJ AVIC 2018, pp. 57-60, Oct. 31-Nov. 2, Chiang Mai, Thailand.

  35. M. Han, Y. Takahashi, and T. Sekine, "A performance comparison of adiabatic logic circuits," Proc. IEEJ AVIC 2018, pp. 149-152, Oct. 31-Nov. 2, Chiang Mai, Thailand.

  36. R. Ito, Y. Takahashi, and T. Sekine, "Adiabatic FinFET 10T-SRAM with virtual ground concept," Proc. IEEJ AVIC 2018, pp. 153-156, Oct. 31-Nov. 2, Chiang Mai, Thailand.

  37. H. Matsumoto, Y. Takahashi, and T. Sekine, "Comparison of performance between different CMOS circuits using suspended-gate FET model," Proc. IEEJ AVIC 2018, pp. 157-160, Oct. 31-Nov. 2, Chiang Mai, Thailand.

  38. T. Tanaka, Y. Takahashi, and T. Sekine, "Adiabatic FinFET SRAM with drowsy cache," Proc. IEEJ AVIC 2018, pp. 161-164, Oct. 31-Nov. 2, Chiang Mai, Thailand.

  39. Y. Masaki, and Y. Takahashi, "Diode based adiabatic logic with feedback circuit in countermeasure against power analysis attacks," Proc. IEEJ AVIC 2018, pp. 165-168, Oct. 31-Nov. 2, Chiang Mai, Thailand.

  40. X. Chen, T. Sekine, and Y. Takahashi, "Estimation of induced positions of external electromagnetic fields by the waveform at both ends of transmission line," Proc. IEEE EMC/APEMC 2018, pp. 654-659, May 14-17, Singapore, Singapore.

  41. Y. Kojima, T. Sekine, Y. Takahashi, N. Maeda, S. Fukui, and Y. Ishikawa, "Partial and indirect non-reciprocal S-parameter measurement for (m+n)-port fixture with DUT," Proc. IEEE EMC/APEMC 2018, pp. 713-717, May 14-17, Singapore, Singapore.

  42. X. Chen, T. Sekine, and Y. Takahashi, "Estimation of induced positions of external electromagnetic fields by the waveform at both ends of transmission line," Proc. KIEES/IEICE KJMW 2017, Session Measurement Technique, Dec. 11-12, Tokyo, Japan.

  43. Y. Takahashi, T. Sekine, and M. Yokoyama, "A verification of resonant clock driver design for the IoT era," Proc. IEEE IMPACT 2017, pp. 492-494, Oct. 24-27, Taipei, Taiwan.

  44. N. Maeda, S. Fukai, T. Sekine, and Y. Takahashi, "An indirect measurement method for S-Parameters which is based on reduction to eigenvalue problem," Proc. IEEE EPEPS 2017, 4 pages, Oct. 15-18, San Jose, CA.

  45. Y. Kojima, T. Sekine, and Y. Takahashi, "Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture," Proc. IEEE ECCTD 2017, pp. 1-4, Sept. 4-6, Catania, Italy.

  46. Y. Takahashi, T. Sekine, and M. Han, "Operational amplifier based LC resonant circuit for adiabatic logic," Proc. IEEE MIXDES 2017, pp. 110-113, June 22-24, Bydgoszcz, Poland.

  47. M. Han, Y. Takahashi, and T. Sekine, "Low power adiabatic logic based on 2PC2AL," Proc. IEEE ICICDT 2017, pp. 1-4, May 23-25, Austin TX.

  48. Y. Matsushita, T. Sekine, and Y. Takahashi, "A modeling method of lossy transmission-line using step-response obtained by slow rising waveform," Proc. PIERS 2017, May 22-25, St. Petersburg, Russia.

  49. Y. Kojima, T. Sekine, and Y. Takahashi, "Number of calibration loads and degree of freedom of fixture's T-parameter for indirect S-parameter estimation," Proc. PIERS 2017, May 22-25, St. Petersburg, Russia.

  50. Y. Takahashi, T. Sekine, and M. Yokoyama, "Simulation and verification of active matrix organic light-emitting diode display driver using adiabatic switching principle," Proc. IEEE IMPACT 2016, pp. 414-416, Oct. 26-28, Taipei, Taiwan.

  51. S. Ohno, Y. Takahashi, and T. Sekine, "Low power adiabatic cascade logic using FinFET," Proc. IEEJ AVIC 2016, pp. 117-122, Aug. 24-26, Boston MA.

  52. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "An indirect measurement method for multiport S-Parameters with reduced number of measurements," Proc. IEEE EMC 2016, pp. 108-113, July 25-29, Ottawa, Canada.

  53. M. Sakai, T. Sekine, and Y. Takahashi, "Investigation of wirelessly powered circuit for low-power adiabatic logic circuits," Proc. IEEE APMC 2015, vol. 2, pp. 1-3, Dec. 6-9, Nanjing, China.

  54. R. Sarmento, and Y. Takahashi, "Power saving analysis of step-down buck converter using adiabatic switching principle," Proc. IEEE ISPACS 2015, pp. 346-350, Nov. 9-12, Bali, Indonesia.

  55. Y. Takahashi, "Vibration reliability characteristics of board-to-board connector pins," Proc. IEEE IMPACT 2015, pp. 313-314, Oct. 21-23, Taipei, Taiwan.

  56. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "An improved wstimation method of 4 port S-parameters with 2 port measurements," Proc. IEEE ECCTD 2015, Session 16B: RF, 4 pages, Aug. 24-26, Trondheim, Norway.

  57. T. Matsubara, T. Sekine, and Y. Takahashi, "Simultaneous approximation method of attenuation and group delay characteristics for coupled resonators filter," Proc. PIERS 2015, p. 1994, July 6-9, Prague, Czech Republic.

  58. S. Ohno, T. Sekine, and Y. Takahashi, "An estimation method for 2-port S-parameters using cable or jig with leakage," Proc. PIERS 2015, p. 2006, July 6-9, Prague, Czech Republic.

  59. S. Ohno, T. Sekine, and Y. Takahashi, "An estimation method for 2-port S-parameters using 4-port connection circuit with leakage couplings," Proc. IEICE/IEIE/ECTI ITC-CSCC 2015, June 29-July 2, Seoul, Korea.

  60. T. Matsubara, T. Sekine, and Y. Takahashi, "New approach for simultaneous approximation of attenuation and group delay characteristics for coupled resonators filter," Proc. IEICE/IEIE/ECTI ITC-CSCC 2015, June 29-July 2, Seoul, Korea.

  61. K. Kato, Y. Takahashi, and T. Sekine, "A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic," Proc. IEEE NEWCAS 2015, Session 8B: Digital Circuits and Architectures for Processing, 4 pages, June 7-10, Grenoble, France.

  62. S. Ohno, T. Sekine, and Y. Takahashi, "An estimation method for 2-port S-parameters using jig with leakage," Proc. KIEES/IEICE KJMW 2014, Session TH_5B Characterization Techniques, 2 pages, Dec. 4-5, Suwon, Korea.

  63. C. Monteiro, Y. Takahashi, and T. Sekine, "Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation," Proc. IEEE APCCAS 2014, pp. 121-124, Nov. 17-20, Okinawa, Japan.

  64. K. Kato, Y. Takahashi, and T. Sekine, "Skey tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic," Proc. IEEE APCCAS 2014, pp. 495-498, Nov. 17-20, Okinawa, Japan.

  65. H. Ogata, Y. Takahashi, and T. Sekine, "Power dissipation analysis of memristor for low power integrated circuit applications," Proc. IEEE APCCAS 2014, pp. 627-630, Nov. 17-20, Okinawa, Japan.

  66. Y. Takahashi, T. Sekine, and M. Yokoyama, "Memristor SPICE model with Tukey window function for stable analysis," Proc. IEEE IMPACT-EMAP 2014, pp. 723-726, Oct. 22-24, Taipei, Taiwan.

  67. N. A. Nayan, A. M. Ikhsan, and Y. Takahashi, "Using ZigBee communication technology in a smart home wireless sensor network," Proc. ICMTSET 2014, pp. 19-25, Sept. 10-11, Dubai, UAE.

  68. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "S-parameter estimation for a multiport connection and a multiport device with non-common ground," Proc. EMC Europe 2014, pp. 838-843, Sept. 1-4, Gothenburg, Sweden.

  69. C. Monteiro, Y. Takahashi, and T. Sekine, "Process variation verification of low-power secure CSSAL AES S-box," Proc. IEEE MWSCAS 2014, pp. 21-24, Aug. 3-6, College Station, TX.

  70. S. Ohno, T. Sekine, and Y. Takahashi, "An estimation method for S-parameters of 4-port circuit by 2-port measurements," Proc. IEICE/IEIE/ECTI ITC-CSCC 2014, pp. 612-613, July 1-4, Phuket, Thailand.

  71. T. Matsubara, T. Sekine, and Y. Takahashi, "Rational function approximation of non-minimum phase filter characteristics by vector fitting," Proc. IEICE/IEIE/ECTI ITC-CSCC 2014, pp. 625-626, July 1-4, Phuket, Thailand.

  72. K. Kato, Y. Takahashi, and T. Sekine, "Two phase clocking subthreshold adiabatic logic," Proc. IEEE ISCAS 2014, pp. 598-601, June 1-5, Melbourne, Australia.

  73. C. Monteiro, Y. Takahashi, and T. Sekine, "An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic," Proc. IEEE ISCAS 2014, pp. 826-829, June 1-5, Melbourne, Australia.

  74. N. Maeda, S. Fukui, T. Murakami, T. Naito, T. Sekine, and Y. Takahashi, "S-parameter estimation for the components in automotive high-voltage units with partial measurements," Proc. IEICE EMC Tokyo 2014, pp. 461-464, May 12-16, Tokyo, Japan.

  75. N. Maeda, S. Fukai, T. Naoi, K. Ichikawa, T. Sekine, and Y. Takahashi, "Mathematics of 2r-port S-parameter estimation by the r-port measurements," Proc. IEEE EDAPS 2013, pp. 270-273, Dec. 12-15, Nara, Japan.

  76. T. Sekine and Y. Takahashi, "Investigation of metamaterial with extended constitutive relationships by using transmission line circuit theory," Proc. IEEE APMC 2013, pp. 1212-1214, Nov. 5-8, Seoul, Korea.

  77. Y. Takahashi, H. Sato, and T. Sekine, "Design and reliability analysis of voltage reference circuit in 180 nm CMOS process," Proc. IEEE IMPACT-IAAC 2013, pp. 480-483, Oct. 22-25, Taipei, Taiwan.

  78. C. Monteiro, Y. Takahashi, and T. Sekine, "Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18 µm CMOS technology," Proc. IEEE ECCTD 2013, Digital Circuit Design (USB), 4 pages, Sept. 8-12, Dresden, Germany.

  79. N. Maeda, S. Fukai, K. Ichikawa, K. Sakurai, T. Sekine, and Y. Takahashi, "An estimation method for the 3 Port S-parameters with 1 port measurements," Proc. IEEE ECCTD 2013, Analog RF Circuits & Design (USB), 4 pages, Sept. 8-12, Dresden, Germany.

  80. N. Maeda, S. Fukai, K. Ichikawa, K. Sakurai, T. Sekine, and Y. Takahashi, "An estimation method for the n port S parameters with n-1 port measurements," Proc. EMC Europe 2013, pp. 348-353, Sept. 2-6, Brugge, Belgium.

  81. C. Monteiro, Y. Takahashi, and T. Sekine, "Low power bit-parallel cellular multiplier implementation in secure dual-rail adiabatic logic," Proc. IACSIT ICCSS 2013, pp. 329-332, Aug. 10-11, Barcelona, Spain.

  82. C. Monteiro, Y. Takahashi, and T. Sekine, "Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks," Proc. IEEE TSP 2013, pp. 732-736, July 2-4, Roma, Italy.

  83. R. Date, T. Sekine, and Y. Takahashi, "A method to estimate the position of the noise source on the transmission line that is induced by external electromagnetic field," Proc. IEICE/IEEK/ECTI ITC-CSCC 2013, pp. 212-213, June 30-July 3, Yeosu, Korea.

  84. L. Zhao, T. Sekine, and Y. Takahashi, "Low power CMOS logic circuits using quasi adiabatic switching principle," Proc. IEICE/IEEK/ECTI ITC-CSCC 2013, pp. 285-286, June 30-July 3, Yeosu, Korea.

  85. C. Monteiro, Y. Takahashi, and T. Sekine, "Low power secure AES S-box using adiabatic logic circuit," Proc. IEEE FTFC 2013, Regular session 3 (USB), 4 pages, June 20-21, Paris, France.

  86. C. Monteiro, Y. Takahashi, and T. Sekine, "DPA resistance of charge-sharing symmetric adiabatic logic," Proc. IEEE ISCAS 2013, pp. 2581-2584, May 19-23, Beijing, China.

  87. C. Monteiro, Y. Takahashi, and T. Sekine, "Low power bit-parallel multiplier over GF(24) using CSSAL for cryptographic hardware implementation," Proc. IEEE Coolchips XVI, Poster session, 1 page, April 17-19, Yokohama, Japan.

  88. C. Monteiro, Y. Takahashi, and T. Sekine, "Secure charge-sharing symmetric adiabatic logic implementation in AES S-Box architecture for smart card," Proc. IEEE ICEIC 2013, pp. 304-305, Jan. 30-Feb. 2, Bali, Indonesia.

  89. K. Murasawa, T. Sekine, and Y. Takahashi, "Investigation of the methods of improving group delay characteristic using complex transmission zeros for coupled resonators filter," Proc. IEEE APMC 2012, pp. 670-672, Dec. 4-7, Kaohsiung, Taiwan.

  90. Y. Urata, Y. Takahashi, T. Sekine, and N. A. Nayan, "A low-power sense amplifier for adiabatic memory using memristor," Proc. IEEE APCCAS 2012, pp. 112-115, Dec. 2-5, Kaohsiung, Taiwan.

  91. Y. Takahashi, Z. Luo, T. Sekine, N. A. Nayan, and M. Yokoyama, "2PCDAL: Two-phase clocking dual-rail adiabatic logic," Proc. IEEE APCCAS 2012, pp. 124-127, Dec. 2-5, Kaohsiung, Taiwan.

  92. Y. Takahashi, T. Sekine, N. A. Nayan, and M. Yokoyama, "Power-saving analysis of adiabatic logic in subthreshold region," Proc. IEEE ISPACS 2012, pp. 590-594, Nov. 4-7, Tamsui, Taiwan.

  93. C. Monteiro, Y. Takahashi, and T. Sekine, "A comparison of cellular multiplier cell using secure adiabatic logics," Proc. IEICE/IEEK/ECTI ITC-CSCC 2012, E-M2-03 (CD-ROM), 4 pages, July 15-18, Hokkaido, Japan.

  94. Y. Urata, Y. Takahashi, and T. Sekine, "A sense amplifier for memristor CAM with adiabatic driving," Proc. IEICE/IEEK/ECTI ITC-CSCC 2012, P-T2-03 (CD-ROM), 4 pages, July 15-18, Hokkaido, Japan.

  95. Z. Luo, Y. Takahashi, and T. Sekine, "Mod-4N2P2D: Diode-based dual-rail adiabatic logic with sinusoidal power supply," Proc. IEICE/IEEK/ECTI ITC-CSCC 2012, P-T2-08 (CD-ROM), 3 pages, July 15-18, Hokkaido, Japan.

  96. T. Sekine, Y. Kawasaki, and Y. Takahashi, "Consideration of metamaterial transmission line with extended constitutive relationships by using circuit theory," Proc. PIERS 2012, March 27-30, Kuala Lumpur, Malaysia.

  97. H. Komiyama, Y. Takahashi, and T. Sekine, "Low-power adiabatic SRAM," Proc. IEEE ISPACS 2011, 4 pages (DVD), Dec. 7-9, Chiang-Mai, Thailand. (PDF File: 173kB, MD5: 7ea608bfaeae9914572d129f8049cd57) [copyright notice]

  98. C. Monteiro, Y. Takahashi, and T. Sekine, "Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card," Proc. IEEE ISPACS 2011, 5 pages (DVD), Dec. 7-9, Chiang-Mai, Thailand. (PDF File: 346kB, MD5: 96d5fb7a9a0744d0169e772d304505cc) [copyright notice]

  99. Y. Takahashi, Y. Urata, T. Sekine, N. A. Nayan, and M. Yokoyama, "Memristor 1T-SRAM with adiabatic driving," Proc. IEEE IEDMS 2011, 4 pages (USB memory), Nov. 17-18, Taipei, Taiwan. (PDF File: 164kB, MD5: d0f609952692367497ee71b2c6dbd9dc) [copyright notice]

  100. Y. Takahashi, T. Sekine, and M. Yokoyama, "Improved local horizontal and vertical common subexpression elimination method for constant multiple multiplication," Proc. Workshop SASIMI 2010, pp. 48-53, Oct. 18-19, Taipei, Taiwan. (PDF File: 192kB, MD5: b7157680f379d9769a1d4b41ceb0bf5c)

  101. N. A. Nayan, Y. Takahashi, and T. Sekine, "4×4-bit array two phase clock adiabatic static CMOS logic multiplier with new XOR," Proc. IEEE/IFIP VLSI SoC 2010, pp. 364-368, Sept. 27-29, Madrid, Spain. (PDF File: 432kB, MD5: 616ab5f8ef220bcf876b8a0c4499756a) [copyright notice]

  102. Y. Tomita, Y. Takahashi, and T. Sekine, "Adiabatic array logic," Proc. IEEE ICSES 2010, pp. 269-272, Sept. 7-10, Gliwice, Poland. (PDF File: 171kB, MD5: b2e8704eb2eb69ce339db1a048263d7d) [copyright notice]

  103. N. A. Nayan, Y. Takahashi, and T. Sekine, "XOR evaluation for 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier," Proc. IEEE MWSCAS 2010, pp. 825-828, Aug. 1-4, Seattle, WA. (PDF File: 382kB, MD5: a061e0e1c1f469b6822bc478316f49f8) [copyright notice]

  104. N. A. Nayan, Y. Takahashi, and T. Sekine, "Low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier," Proc. IEICE/IEEK/ECTI ITC-CSCC 2010, pp. 296-299, July 4-7, Pattaya, Thailand. (PDF File: 443kB, MD5: a60b3abb2376ad22959063b23d05d09a)

  105. Y. Takahashi, T. Sekine, and M. Yokoyama, "A comparison of adiabatic logic as a countermeasures against power analysis attacks," Proc. IEEE ICSSE 2010, pp. 615-618, July 1-3, Taipei, Taiwan. (PDF File: 144kB, MD5: a229a5bd247e60db2763a20fb7b13c28) [copyright notice]

  106. N. A. Nayan, Y. Takahashi, and T. Sekine, "4×4-bit array multiplier using two phase clocked adiabatic static CMOS logic," Proc. IEEE Coolchips XIII, p. 193, April 14-16, Yokohama, Japan. (PDF File: 98kB, MD5: 71e82c1f88143a6ce6b94c67605310e1) [copyright notice]

  107. K. Kato, Y. Takahashi, and T. Sekine, "A new horizontal and vertical common subexpression elimination method for multiple constant multiplication," Proc. IEEE ICECS 2009, pp. 124-127, Dec. 13-16, Hammamet, Tunisia. (PDF File: 204kB, MD5: 969625bf7fd2b8747fd16a7a2bdb288c) [copyright notice]

  108. N. A. Nayan, Y. Takahashi, and T. Sekine, "Fundamental logics based on two phase clocked adiabatic static CMOS logic," Proc. IEEE ICECS 2009, pp. 503-506, Dec. 13-16, Hammamet, Tunisia. (PDF File: 264kB, MD5: 6cd3ead7ef61c485db069cf682840266) [copyright notice]

  109. N. A. Nayan, Y. Takahashi, and T. Sekine, "4-bit ripple carry adder using two phase clocked adiabatic static CMOS logic," Proc. IEEE TENCON 2009, THU4.P.16 (CD-ROM), 6 pages, Nov. 23-26, Singapore, Singapore. (PDF File: 812kB, MD5: 7f222a549d9ac12403fb3e523adf5a67) [copyright notice]

  110. N. A. Nayan, Y. Takahashi, and T. Sekine, "Two phase clocked adiabatic static CMOS logic," Proc. IEEE ISSoC 2009, pp. 83-86, Oct. 5-7, Tampere, Finland. (PDF File: 368kB, MD5: 55297ee7907ace8c2bd49d717819b726) [copyright notice]

  111. T. Hirose, T. Sekine, and Y. Takahashi, "Modeling of dielectric dispersive characteristics and the step response of transmission line," Proc. IEEE CEEM 2009, pp. 34-37, Sept. 19-20, Xi'an, China.

  112. T. Fukatsu, T. Sekine, and Y. Takahashi, "A comparison of incorporation of dissipation in the FDTD analysis of transmission lines using stability analysis," Proc. IEEE CEEM 2009, pp. 58-61, Sept. 19-20, Xi'an, China.

  113. N. A. Nayan, Y. Takahashi, and T. Sekine, "4-bit ripple carry adder of two-phase clocked adiabatic static CMOS Logic: A comparison with static CMOS," Proc. IEEE ECCTD 2009, pp. 65-68, Aug. 23-27, Antalya, Turkey. (PDF File: 270kB, MD5: 47ee59862cdf4d2af01a56cd7d3ecb44) [copyright notice]

  114. Y. Takahashi, S. Nagano, N. A. Nayan, T. Sekine, and M. Yokoyama, "On Chip LC resonator circuit using an active inductor for adiabatic logic," Proc. IEEE MWSCAS 2009, pp. 1171-1174, Aug. 2-5, Cancun, Mexico. (PDF File: 200kB, MD5: 09931e2ed1deccb38b37ac2b4753ae3a) [copyright notice]

  115. N. A. Nayan, Y. Takahashi, and T. Sekine, "Adiabatic logic versus CMOS for low power applications," Proc. IEICE/IEEK/ECTI ITC-CSCC 2009, pp. 302-305, July 5-8, Jeju, Korea. (PDF File: 268kB, MD5: 65396f57c6d5a5389d5d303403181404)

  116. T. Sekine, and Y. Takahashi, and T. Nakamura, "Transparent and double-sided wave absorber with specified reflection and transmission coefficients," Proc. EMC Europe Workshop 2009, Session 4: Materials and Measurements (CD-ROM), 3 pages, June 11-12, Athens, Greece.

  117. K. Watanabe, T. Sekine, and Y. Takahashi, "A FDTD method for nonuniform transmission line analysis using Yee's-lattice and wavelet expansion," Proc. IEEE MTTS IMWS 2009, pp. 83-86, Feb 19-20, Guadalajara, Mexico.

  118. Y. Takahashi, T. Sekine, and M. Yokoyama, "Theoretical analysis of power clock generator based on the switched capacitor regulator for adiabatic CMOS logic," Proc. IEEE EAMTA/CAMTA 2008, pp. 17-22, Sept. 18-19, Buenos Aires, Argentine. (PDF File: 356kB, MD5: d9f3af7d5ce5d39cbc667c50e814eea3) [copyright notice]

  119. Y. Takahashi, T. Sekine, and M. Yokoyama, "A comparison of multiplierless multiple constant multiplication using common subexpression elimination method," Proc. IEEE MWSCAS 2008, pp. 298-301, Aug. 10-13, Knoxville, TN. (PDF File: 136kB, MD5: 2a81217f1e4ab5dfa5e5548055c94592) [copyright notice]

  120. K.Watanabe, T. Sekine, Y. Takahashi, and K. Kobayashi, "Analysis of nonuniform transmission line equations using Yee-lattice and wavelet expansion," Proc. IEICE PPEMC 2008, pp. 93-94, May 15-16, Tokyo, Japan.

  121. Y. Takahashi, D. Tsuzuki, T. Sekine, and M. Yokoyama, "Design of a 16-bit RISC CPU core in a two phase drive adiabatic dynamic CMOS logic," Proc. IEEE TENCON 2007, WeSC-O2.1 (CD-ROM), 4 pages, Oct. 30-Nov. 2, Taipei, Taiwan. (PDF File: 181kB, MD5: 14dec69f005db35f22b3e2703225cf85) [copyright notice]

  122. T. Sekine, D. Ichikawa, Y. Takahashi, and K. Kobayashi, "A lossy interconnect modeling in both the time and the frequency domain using a synthesis method of lossy nonuniform transmission line," Proc. EMC Zurich 2007, pp. 65-68, Sep. 24-28, Munich, Germany.

  123. Y. Takahashi, T. Sekine, and M. Yokoyama, "A 4-bit multiplier using a two phase drive adiabatic dynamic CMOS logic," Proc. IEICE/IEEK/ECTI ITC-CSCC 2007, vol. 1, pp. 205-206, July 8-11, Busan, Korea. (PDF File: 137kB, MD5: 000480685ab75b89597c9255b6b7ab67)

  124. D. Ichikawa, T. Sekine, Y. Takahashi, and K. Kobayashi, "A time domain modeling of lossy interconnect using nonuniform transmission line with frequency independent distributed parameters," Proc. IEICE/IEEK/ECTI ITC-CSCC 2007, vol. 3, pp. 1053-1054, July 8-11, Busan, Korea.

  125. T. Sekine, N. Ichimura, and Y. Takahashi, and K. Kobayashi, "Double-sided and transparent two-layer wave absorber with specified reflection and transmission coefficients," Proc. IEICE/IEEK/ECTI ITC-CSCC 2007, vol. 1, pp. 1-2, July 8-11, Busan, Korea (Invited Paper).

  126. T. Sekine, D. Ichikawa, and Y. Takahashi, and K. Kobayashi, "A lossy interconnect modeling by S parameters measurements using a synthesis method of lossy nonuniform transmission line," Proc. EMC Europe Workshop 2007, pp. 116-121, June 14-15, Paris, France.

  127. Y. Takahashi, Y. Fukuta, T. Sekine, and M. Yokoyama, "2PADCL: Two phase drive adiabatic dynamic CMOS logic," Proc. IEEE APCCAS 2006, pp. 1486-1498, Dec. 4-7, Singapore, Singapore. (PDF File: 208kB, MD5: 2050e912f4730769a83b9df9ae72e7d7) [copyright notice]

  128. T. Sekine, Y. Horibe, Y. Takahashi, and K. Kobayashi, "An extended method of characteristics for lossy nonuniform transmission line analysis and its numerical stability," Proc. EMC Europe 2006, vol. 2, pp. 1129-1134, Sept. 4-8, Barcelona, Spain.

  129. Y. Takahashi, Y. Fukuta, T. Sekine, and M. Yokoyama, "2PADCL: Two phase drive adiabatic dynamic CMOS logic," Proc. IEICE/IEEK/ECTI ITC-CSCC 2006, vol. 1, pp. 41-44, July 10-13, Chiang-Mai, Thailand. (PDF File: 163kB, MD5: 4a7fb9ff3bfb35a603a1d76017d3563a)

  130. Y. Takahashi and M. Yokoyama, "A 70MHz multiplierless FIR Hilbert transformer in 0.35 µm CMOS standard-cell technology," Circuit Exhibition Catalogue of ESSCIRC 2005, p. 25, Sept. 12-16, Grenoble France. (PDF File: 207kB, Poster, MD5: 26cf9d89612440fab49abf5c2d2a7b44)

  131. T. Sekine, Y. Takahashi, and K. Kobayashi, "A method of the time-domain synthesis for lossy nonuniform transmission line using reflection and transmission response at both ends," Proc. IEEE MWSCAS 2005, pp. 255-258, Aug. 7-10, Ohio, USA.

  132. Y. Takahashi, T. Sekine, and M. Yokoyama, "A 70 MHz multiplierless FIR Hilbert transformer in 0.35 µm CMOS," Proc. IEICE/IEEK/ECTI ITC-CSCC 2005, vol. 3, pp. 947-948, July 4-7, Jeju, Korea. (PDF File: 139kB, MD5: ed19fe56e4c38c19331467c17116d63a)

  133. Y. Takahashi and M. Yokoyama, "New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination," Proc. IEEE ISCAS 2005, pp. 1445-1448, May 23-26, Kobe, Japan. (PDF File: 139kB, MD5: 950f782e04314bde5023e67059a0405e) [copyright notice]

  134. Y. Takahashi, K. Takahashi, and M. Yokoyama, "Synthesis of multiplierless FIR filter by efficient sharing of horizontal and vertical common subexpression elimination," Proc. IEICE/IEEK ITC-CSCC 2004, pp. 7C2L-4-1 - 7C2L-4-4, July 6-8, Matsushima, Japan. (PDF File: 127kB, MD5: 7e36644a9f532204596c6b5df30399c9)

  135. T. Matsuda, Y. Takahashi, K. Takahashi, M. Yokoyama, and M. Mizunuma, "A matched-filterless spread spectrum communication system," Proc. IEICE/IEEK ITC-CSCC 2004, pp. 6A2L-4-1 - 6A2L-4-4, July 6-8, Matsushima, Japan. (PDF File: 116kB, MD5: 9313de2d6bb97b9c668af42dd61323ad)

  136. D. Miura, Y. Takahashi, K.Takahashi, M. Yokoyama, and M.Mizunuma, "CMOS analog matched filter for DS-CDMA system based on operational amplifier," Proc. IEICE/IEEK ITC-CSCC 2004, pp. 8C2L-1-1 - 8C2L1-4, July 6-8, Matsushima, Japan. (PDF File: 1424kB, MD5: 16a1d87cafcd20d442ca0aab5ea256f8)

  137. Y. Takahashi, K. Takahashi, K. Shouno, and M. Yokoyama, "A partial local search algorithm for the design of multiplierless FIR digital filters with CSD coefficients and its FPGA implementation," Proc. IEEE ISPACS 2003, pp. 757-762, Dec. 7-10, Awaji-island, Japan. (PDF File: 368kB, MD5: 6e9cb154f2d890d3c1eea7018ccab1f8) [copyright notice]

  138. Y. Takahashi, M. Yokoyama, K. Shouno, M.Mizunuma, and K.Takahashi, "A 1bit carry propagate free adder/subtracter VLSI using adiabatic dynamic CMOS logic circuit technology," Proc. IEICE/IEEK ITC-CSCC 2002, pp. 349-352, July 16-19, Phuket, Thailand. (PDF File: 226kB, MD5: 1bbde497c3233d36bd8fc526aad84161)

  139. Y. Takahashi, T. Kitajima, and K. Takahashi, "Hilbert transformer design using CSD FIR filter," Proc. IEICE/IEEK ITC-CSCC 2001, pp. 921-924, July 10-12, Tokushima Japan. (PDF File: 104kB, MD5: d1b3621261ce99297c54edffcfd57614)

[Domestic conference paper]

  1. M. Shibata, and Y. Takahashi, "A study on applying Dickson rectifier to adiabatic logic circuit," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-24, pp. 53-56 (ECT-24-021), March 2024.

  2. R. Iwata, and Y. Takahashi, "A design of wideband and low-noise RGC-TIA," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-24, pp. 57-60 (ECT-24-022), March 2024.

  3. K. Tominaga, and Y. Takahashi, "Proposal for an AVCF-type low-power AFE TIA using 65-nm CMOS technology," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-23, pp. 31-35 (ECT-23-059), Nov. 2023.

  4. Y. Takahashi, "A simulation comparison of chaotic circuits under different memristor SPICE models," IEICE Technical Report, vol. 123, no. 203, NLP2023-29, pp. 1-4, Oct. 2023.

  5. Y. Takahashi, D. Ito, M. Nakamura, A. Tsuchiya, T. Inoue, and K. Kishine, "Regulated cascode transimpedance amplifier with local feedback loop in 65-nm CMOSprocess," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-22, pp. 51-55 (ECT-22-032), June 2022.

  6. Y. Takahashi, D. Ito, M. Nakamura, A. Tsuchiya, T. Inoue, and K. Kishine, "A design of multi-stage RGC-TIA circuit having a local feedback," 2022 Proceedings IEICE General Conference (Engineering Sciences/NOLTA Society Section), vol. 2022, no.1, p. 4 (A-1-4), IEICE, March 2022.

  7. D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya, and K. Kishine, "Burst-mode driver circuit using on-chip bias tee for optical packet communication," 2022 Proceedings IEICE General Conference (Engineering Sciences/NOLTA Society Section), vol. 2022, no.1, p. 7 (A-1-7), IEICE, March 2022.

  8. T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura, "A 25-Gb/s laser driver with variable output impedance in 65-nm CMOS process," 2022 Proceedings IEICE General Conference (Engineering Sciences/NOLTA Society Section), vol. 2022, no.1, p. 8 (A-1-8), IEICE, March 2022.

  9. A. Tsuchiya, T. Inoue, Y. Takahashi, D. Ito, K. Kishine, and M. Nakamura, "Impact of input impedance of transimpedance amplifier with transmission-line connection to photodetector," 2022 Proceedings IEICE General Conference (Electronics Society Section), vol. 2022, no.2, p. 48 (C-12-10), IEICE, March 2022.

  10. T. Fukuura, and Y. Takahashi, "A design examination of RGC trans-impedance amplifier using active inductor," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-21, pp. 1-4 (ECT-21-090), Dec. 2021.

  11. J. Liu, and Y. Takahashi, "Evaluation of simulation of adiabatic SRAM-PUF," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-21, pp. 53-57 (ECT-21-076), Dec. 2021.

  12. I. Okuda, and Y. Takahashi, "Adiabatic PUF circuit based on QUALPUF," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-21, pp. 59-62 (ECT-21-077), Dec. 2021.

  13. R. Ito, and Y. Takahashi, "Evaluation on adiabatic Fin-FET 10T-SRAM with virtual ground structure," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-21, pp. 63-67 (ECT-21-078), Dec. 2021.

  14. Y. Takahashi, and R. Ohashi, "Resistance evaluation of cryptographic adiabatic logic circuit with bootstrap structure," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-20, pp. 1-6 (ECT-20-075), Dec. 2020.

  15. H. Koyasu, and Y. Takahashi, "Design and evaluation of galois field multiplier using adiabatic logic," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-20, pp. 7-12 (ECT-20-076), Dec. 2020.

  16. K. Ogura, and Y. Takahashi, "Evaluation of uniquness and reliability of PUF circuit using adiabatic logic," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-20, pp. 13-17 (ECT-20-077), Dec. 2020.

  17. T. Sekine, Y. Takahashi, N. Maeda, S. Fukui, Y. Ishikawa, and K. Oyama, "S-parameter measurement method where calibration and measurement are performed simultaneously," IEICE Technical Report, vol. 119, no. 346, MW2019-118, pp. 1-4, Dec. 2019.

  18. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "Recursive method for S-parameter indirect measurement," IEICE Technical Report, vol. 119, no. 346, MW2019-119, pp. 5-10, Dec. 2019.

  19. T. Sekine, and Y. Takahashi, "Basic considerations for activation of negative group delay circuit consisting of resonators," IEICE Technical Report, vol. 119, no. 237, CAS2019-27, pp. 23-27, Oct. 2019.

  20. Y. Takahashi, and H. Koyasu, "Evaluation of post-layout simulation of adiabatic SRAM PUF," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-19, pp. 47-50 (ECT-19-058), Sept. 2019.

  21. T. Ikkai, T. Sekine, and Y. Takahashi, "Negative group delay circuit using nonuniform transmission line," IEICE Technical Report, vol. 119, no. 12, MW2019-5, pp. 21-26, Jan. 2019.

  22. T. Sekine, and Y. Takahashi, "Partial measurement and indirect measurement of S-parameters connecting DUT and known loads to different ports," IEICE Technical Report, vol. 118, no. 403, MW2018-138, pp. 13-16, Jan. 2019.

  23. N. Maeda, S. Fukai, T. Sekine, and Y. Takahashi, "Indirect measurement method for S-parameters of reciprocal circuits with measuring a minor number of ports," IEICE Technical Report, vol. 118, no. 363, EMCJ2018-90, pp. 19-23, Dec. 2018.

  24. T. Sekine, Y. Takahashi, N. Maeda, S. Fukai, Y. Ishikawa, and K. Oyama, "A S-parameter measurement method for circuit consisting of analog IC and its power supply IC," IEICE Technical Report, vol. 118, no. 363, EMCJ2018-92, pp. 51-56, Dec. 2018.

  25. H. Koyasu, and Y. Takahashi, "Evaluation of power analysis attacks on cryptographic circuit using adiabatic logic," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 1-4 (ECT-18-061), Oct. 2018.

  26. R. Ohashi, and Y. Takahashi, "Cryptographic adiabatic logic with bootstrap circuit structure," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 5-9 (ECT-18-062), Oct. 2018.

  27. Y. Masaki, and Y. Takahashi, "Performance evaluation of S-Box using diode-based adiabatic logic," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 11-14 (ECT-18-063), Oct. 2018.

  28. T. Nishiwaki, Y. Takahashi, and T. Sekine, "A Proposal for adiabatic reversible logic," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 15-19 (ECT-18-064), Oct. 2018.

  29. T. Tanaka, Y. Takahashi, and T. Sekine, "Performance verification of FinFET SRAM with drowsy cache," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 21-24 (ECT-18-065), Oct. 2018.

  30. R. Ito, Y. Takahashi, and T. Sekine, "Evaluation of 10T adiabatic SRAM with virtual ground structure under CMOS process variation," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 25-29 (ECT-18-066), Oct. 2018.

  31. T. Fukuura, and Y. Takahashi, "Shunt-series peaking transimpedance amplifier using active inductor with RGC configuration," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 39-42 (ECT-18-069), Oct. 2018.

  32. R. Tagawa, and Y. Takahashi, "Bandwidth extension of transimpedance amplifier using CMOS negative impedance circuit," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 43-46 (ECT-18-070), Oct. 2018.

  33. H. Matsumoto, and Y. Takahashi, "Verification of suspended-gate FET using capacitance model," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 83-86 (ECT-18-078), Oct. 2018.

  34. T. Sekine, and Y. Takahashi, "," 2018 Proceedings IEICE Society Conference, vol. 2018, pp. ***-*** (BS-3-2), IEICE, Sept. 2018.

  35. T. Sekine, and Y. Takahashi, "Modified vector fitting and its application to both attenuation and group delay characteristics approximation," IEICE Technical Report, vol. 118, no. 104, MW2018-20, pp. 13-18, June 2018.

  36. T. Fukuura, and Y. Takahashi, "A bandwidth extension of transimpedance amplifier using active inductor in shunt and series peaking techniques," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 1-5 (ECT-18-010), March 2018.

  37. R. Tagawa, and Y. Takahashi, "A bandwidth extension of transimpedance amplifier using Linvill's negative impedance converters," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 5-8 (ECT-18-011), March 2018.

  38. M. Han, Y. Takahashi, and T. Sekine, "A comparison of energy dissipation of 4-bit adiabatic multiplier," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 45-48 (ECT-18-019), March 2018.

  39. B. Da Costa, and Y. Takahashi, "A design of trans-impedance amplifier using negative impedance converter," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 49-52 (ECT-18-020), March 2018.

  40. X. Chen, and Y. Takahashi, "Small-signal analysis of trans-impedance amplifier using Mahmoudi-Salama's floating active inductor," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 53-56 (ECT-18-021), March 2018.

  41. H. Koyasu, and Y. Takahashi, "Current path optimized-symmetric pass gate adiabatic logic for cryptographic circuits," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 121-124 (ECT-18-035), March 2018.

  42. Y. Asano, and Y. Takahashi, "Diode based adiabatic logic for cryptographic circuits," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-18, pp. 125-128 (ECT-18-036), March 2018.

  43. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "An indirect measurement method for S-parameters using eigen-relation residing in measured values," IEICE Technical Report, vol. 117, no. 357, EMCJ2017-76, pp. 1-6, Dec. 2017.

  44. Y. Kojima, T. Sekine, and Y. Takahashi, "An indirect S-parameter measurement method of 2-port circuit using (1, 3)-port fixture," IEICE Technical Report, vol. 117, no. 357, EMCJ2017-77, pp. 7-12, Dec. 2017.

  45. Y. Matsushita, T. Sekine, and Y. Takahashi, "Approximation of input and output characteristics of lossy transmission line using vector fitting," IEICE Technical Report, vol. 117, no. 357, EMCJ2017-78, pp. 13-18, Dec. 2017.

  46. M. Han, Y. Takahashi, and T. Sekine, "Evaluation of 4-bit array multiplier of adiabatic logic family," IEICE Technical Report, vol. 117, no. 343, ICD2017-68, pp. 27-30, Dec. 2017.

  47. T. Tanaka, Y. Takahashi, and T. Sekine, "Evaluation of variations and reliabilities of drowsy cache type adiabatic FinFET SRAM," IEICE Technical Report, vol. 117, no. 343, CAS2017-77, pp. 71-74, Dec. 2017.

  48. H. Matsumoto, Y. Takahashi, and T. Sekine, "SPICE model of suspended-gate FET using a new fitting function," IEICE Technical Report, vol. 117, no. 343, CAS2017-78, pp. 75-78, Dec. 2017.

  49. T. Nishiwaki, Y. Takahashi, and T. Sekine, "A proposal for improving security of adiabatic reversible logic based on PADDL," IEICE Technical Report, vol. 117, no. 344, ICD2017-76, pp. 113-117, Dec. 2017.

  50. R. Itoh, Y. Takahashi, and T. Sekine, "Function evaluation of adiabatic FinFET SRAM with virtual ground structure," IEICE Technical Report, vol. 117, no. 344, ICD2017-77, pp. 119-122, Dec. 2017.

  51. X. Chen, Y. Takahashi, and T. Sekine, " Evaluation of wide-band frequency trans-impedance amplifier using active inductors," IEICE Technical Report, vol. 117, no. 344, ICD2017-78, pp. 123-126, Dec. 2017.

  52. Y. Kojima, T. Sekine, and Y. Takahashi, "Estimation of 4 Port S parameter by 1 port measurement and its application to 2 Port indirect measurement," IEICE Technical Report, vol. 117, no. 244, MW2017-82, pp. 1-5, Oct. 2017.

  53. Y. Matsushita, T. Sekine, and Y. Takahashi, "Consideration of step response estimation using band-limited frequency response," IEICE Technical Report, vol. 117, no. 243, EMCJ2017-38, pp. 62-72, Oct. 2017.

  54. R. Wakemoto, Y. Takahashi, and T. Sekine, "SNM, read and wtite characteristics evaluation of Fin-FET SRAM with threshold voltage variation," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-17, pp. 97-100 (ECT-17-114), Oct. 2017.

  55. T. Nishiwaki, Y. Takahashi, and T. Sekine, "Adiabatic reversible logic based on PADDL," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-17, pp. 7-12 (ECT-17-054), IEEJ, July 2017.

  56. R. Itoh, Y. Takahashi, and T. Sekine, "Adiabatic FinFET SRAM with virtual ground structure," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-17, pp. 13-16 (ECT-17-055), IEEJ, July 2017.

  57. H. Matsumoto, Y. Takahashi, and T. Sekine, "SPICE modeling of Suspended-Gate FET and its operation verification," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-17, pp. 57-60 (ECT-17-066), IEEJ, July 2017.

  58. T. Tanaka, Y. Takahashi, and T. Sekine, "Drowsy cache type adiabatic FinFET SRAM," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-17, pp. 61-66 (ECT-17-067), IEEJ, July 2017.

  59. S. Ohno, T. Sekine, and Y. Takahashi, "An indirect S-parameter estimation method for multi-port circuit using S parameters of fixture -In case of the number of measurement ports is equal to the number of DUT ports-," IEICE Technical Report, vol. 117, no. 104, MW2017-29, pp. 43-47, June 2017.

  60. J. Kawahara, Y. Takahashi, and T. Sekine, "Current and energy variation evaluation of S-Box using adiabatic logic," Proceedings IEICE the 30th Workshop on Circuits and Systems, pp. 111-116, May 2017 (Refereed).

  61. Y. Hayashi, Y. Takahashi, and T. Sekine, "Investigation of energy dissipation of diode connected adiabatic logic using FinFET," Proceedings IEICE the 30th Workshop on Circuits and Systems, pp. 117-120, May 2017 (Refereed).

  62. H. Yamamoto, Y. Takahashi, and T. Sekine, "Verification of S-BOX using adiabatic logic families by 65nm SOTB process," Proceedings IEICE the 30th Workshop on Circuits and Systems, pp. 121-126, May 2017 (Refereed).

  63. R. Kakemoto, Y. Takahashi, and T. Sekine, "SNM CreadCwrite characteristics evaluation of Fin-FET SRAM," Proceedings IEICE the 30th Workshop on Circuits and Systems, pp. 127-131, May 2017 (Refereed).

  64. Y. Matsushita, T. Sekine, and Y. Takahashi, "Direct estimation method of input or output response based on step response of circuit," Proceedings IEICE the 30th Workshop on Circuits and Systems, pp. 232-236, May 2017 (Refereed).

  65. Y. Kojima, T. Sekine, and Y. Takahashi, "Degree of freedom of T parameter in indirect S-parameters estimation when the number of ports of measurement and the number of ports of the circuit to be measured are different," Proceedings IEICE the 30th Workshop on Circuits and Systems, pp. 237-242, May 2017 (Refereed).

  66. Y. Matsushita, T. Sekine, and Y. Takahashi, "An direct estimation method of input or output waveform based on step response," 2017 Proceedings IEICE General Conference, vol. 2017, p. 32 (A-1-32), IEICE, March 2017.

  67. Y. Kojima, T. Sekine, and Y. Takahashi, "Number of calibration loads and freedom degree of T-parameter required for indirect S-parameter estimation," 2017 Proceedings IEICE General Conference, vol. 2017, p. 292 (B-4-14), IEICE, March 2017.

  68. Y. Matsushita, T. Sekine, and Y. Takahashi, "Application of an ideal step response estimation using a slowly rising waveform as input to the FDTD method," IEICE Technical Report, vol. 116, no. 467, CAS2016-131, pp. 95-98, Feb. 2017.

  69. Y. Matsushita, T. Sekine, and Y. Takahashi, "Ideal step response estimation method using an input of the slow rising waveform and application to lossy transmission line parameter deriving," IEICE Technical Report, vol. 116, no. 370, EMCJ2016-106, pp. 37-42, Dec. 2016.

  70. Y. Kojima, T. Sekine, and Y. Takahashi, "Investigation of indirect S parameter estimation when the number of ports of measurement and the number of ports of the circuit to be measured are different," IEICE Technical Report, vol. 114, no. 363, MW2016-152, pp. 113-117, Dec. 2016.

  71. Y. Kojima, T. Sekine, and Y. Takahashi, "S-parameter estimation method for multi-port circuit using T parameters of fixture -the number of ports of the measurement and multi-port circuit is not equal-," IEICE Technical Report, vol. 116, no. 253, EMCJ2016-80, pp. 119-124, Oct. 2016.

  72. S. Ohno, Y. Takahashi, and T. Sekine, "Operating margin analysis of 4×4bit multiplier on adiabatic logic using a FinFET," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 26 (A-1-26), IEICE, Sept. 2016.

  73. Y. Hayashi, Y. Takahashi, and T. Sekine, "Investigation of low power consumption of adiabatic logic using FinFET," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 27 (A-1-27), IEICE, Sept. 2016.

  74. R. Wakemoto, Y. Takahashi, and T. Sekine, "Evaluation of static noise margin of FinFET 4T-SRAM," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 28 (A-1-28), IEICE, Sept. 2016.

  75. J. Kawahara, Y. Takahashi, and T. Sekine, "An evaluation of current variation of Adiabatic circuit for smart card," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 31 (A-1-31), IEICE, Sept. 2016.

  76. H. Yamamoto, Y. Takahashi, and T. Sekine, "Verification of application circuit using the adiabatic logic circuit CSSAL by 65nmSOTB process," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 32 (A-1-32), IEICE, Sept. 2016.

  77. Y. Matsushita, T. Sekine, and Y. Takahashi, "An Estimation Method of Ideal Step Response in the Time Domain and High Accuracy TDR Method," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 53 (C-2-43), IEICE, Sept. 2016.

  78. Y. Kojima, T. Sekine, and Y. Takahashi, "S-parameter estimation method for the case that the number of ports of jig for measurements is more than the number of ports of the target multi-port," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 248 (B-4-40), IEICE, Sept. 2016.

  79. X. Chen, T. Sekine, and Y. Takahashi, "Time domain equivalent circuit of the terminated transmission line under the external electromagnetic field," 2016 Proceedings IEICE Society Conference, vol. 2016, p. 266 (B-4-58), IEICE, Sept. 2016.

  80. D. Saito, T. Sekine, and Y. Takahashi, "Extension to the case including the control source of the descriptor system representation of the circuit equations," 2016 Proceedings IEICE Society Conference, vol. 2016, pp. S-23 - S-24 (CS-2-009), IEICE, Sept. 2016.

  81. X. Chen, T. Sekine, and Y. Takahashi, "Estimation of induced positions of external electromagnetic fields on transmission line using time domain measurements," IEICE Technical Report, vol. 116, no. 135, EMCJ2016-47, pp. 19-23, July 2016.

  82. Y. Kojima, T. Sekine, and Y. Takahashi, "Multi-port S-parameter estimation method considering reciprocity of connection circuit," IEICE Technical Report, vol. 116, no. 114, MW2016-33, pp. 15-20, June 2016.

  83. Y. Matsushita, T. Sekine, and Y. Takahashi, "Application to nonuniform transmission line analysis of high accuracy transient analysis method to compensate for the band-limited data so as to satisfy the causality," IEICE Technical Report, vol. 116, no. 114, MW2016-34, pp. 21-26, June 2016.

  84. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "An Indirect Measurement Method for Multiport S-Parameters based on similarity transformation by the transfer coefficient submatrix," IEICE Technical Report, vol. 116, no. 114, MW2016-35, pp. 27-32, June 2016.

  85. D. Saito, T. Sekine, and Y. Takahashi, "A descriptor system representation of circuit equations based on the reduced incidence matrix," IEICE Technical Report, vol. 116, no. 93, CAS2016-5, pp. 23-28, June 2016.

  86. R. Kamada, T. Sekine, and Y. Takahashi, "Equivalence of non-adjacent resonators coupling structure and series-parallel resonators coupling structure," IEICE Technical Report, vol. 116, no. 51, MW2016-12, pp. 15-20, May 2016.

  87. S. Ohno, Y. Takahashi, and T. Sekine, "Power consumption reduction effect of 4×4 bit multiplier using FinFET adiabatic logic by adding reverse bias voltage to back-gate," Proceedings IEICE the 29th Workshop on Circuits and Systems, pp. 1-6, May 2016 (Refereed).

  88. M. Sakai, T. Sekine, and Y. Takahashi, "Improvement of the signal waveforms of the CMOS logic circuit operating by the rectenna for adiabatic circuit," Proceedings IEICE the 29th Workshop on Circuits and Systems, pp. 7-12, May 2016 (Refereed).

  89. J. Kawahara, Y. Takahashi, and T. Sekine, "Current variation evaluation of adiabatic logic circuit for smart card," Proceedings IEICE the 29th Workshop on Circuits and Systems, pp. 48-51, May 2016 (Refereed).

  90. H. Yamamoto, Y. Takahashi, and T. Sekine, "Verification of application circuit using the adiabatic logic circuit CSSAL by 65nmSOTB process," Proceedings IEICE the 29th Workshop on Circuits and Systems, pp. 54-57, May 2016 (Refereed).

  91. Y. Hayashi, Y. Takahashi, and T. Sekine, "Investigation of Improved Output of Adiabatic LogicUsing FinFET," Proceedings IEICE the 29th Workshop on Circuits and Systems, pp. 58-60, May 2016 (Refereed).

  92. D. Saito, T. Sekine, and Y. Takahashi, "A formulation of circuit wquations using descriptor system representation," Proceedings IEICE the 29th Workshop on Circuits and Systems, pp. 255-260, May 2016 (Refereed).

  93. D. Saito, T. Sekine, and Y. Takahashi, "A formulation of circuit equations with descriptor system representation," 2016 Proceedings IEICE General Conference, vol. 2016, p. 1 (A-1-1), IEICE, March 2016.

  94. M. Sakai, T. Sekine, and Y. Takahashi, "A method of improving signal waveform degradation due to signal propagation delay of adiabatic logic," 2016 Proceedings IEICE General Conference, vol. 2016, p. 2 (A-1-2), IEICE, March 2016.

  95. S. Ohno, Y. Takahashi, and T. Sekine, "Power consumption reduction effect of FinFET adiabatic logic by adding reverse bias voltage to back-gate," 2016 Proceedings IEICE General Conference, vol. 2016, p. 3 (A-1-3), IEICE, March 2016.

  96. X. Chen, T. Sekine, and Y. Takahashi, "An estimation method of the induced positions of external electromagnetic fields using the wave form at bot ends transmission line," 2016 Proceedings IEICE General Conference, vol. 2016, p. 383 (B-4-63), IEICE, March 2016.

  97. S. Ouno, T. Sekine, and Y. Takahashi, "Improvement of the estimation method for multi-port S parameters through the connection circuit with unnecessary leakage coupling between the ports," IEICE Technical Report, vol. 115, no. 377, EMCJ2015-100, pp. 63-68, Dec. 2015.

  98. T. Matsubara, T. Sekine, and Y. Takahashi, "A simultaneous characteristics approximation of attenuation and group delay for bandpass filter with asymmetrical attenuation poles," IEICE Technical Report, vol. 115, no. 260, MW2015-103, pp. 29-34, Oct. 2015.

  99. D. Saito, T. Sekine, and Y. Takahashi, "An analysis method of transmission line with local ground based on the state variable approach," IEICE Technical Report, vol. 115, no. 259, EMCJ2015-7, pp. 91-96, Oct. 2015.

  100. S. Ouno, T. Sekine, and Y. Takahashi, "Multi-port S parameter estimation through the connection circuit with unnecessary leakage coupling between the ports," IEICE Technical Report, vol. 115, no. 217, EMCJ2015-54, pp. 7-12, Sept. 2015.

  101. C. Monteiro, Y. Takahashi, and T. Sekine, "Efficient DPA-Resistance verification of CSSAL AES S-box LSI implemented using 0.18 µm CMOS technology," Proceedings IEICE the 28th Workshop on Circuits and Systems, pp. 76-81, Aug. 2015 (Refereed).

  102. K. Kato, Y. Takahashi, and T. Sekine, "An energy consumption analysis of subthreshold adiabatic logic circuit," Proceedings IEICE the 28th Workshop on Circuits and Systems, pp. 82-87, Aug. 2015 (Refereed).

  103. S. Ouno, Y. Takahashi, and T. Sekine, "Power reducing effectiveness of adiabatic logic using FinFET," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-15, no. 3, pp. 77-82 (ECT-15-060), IEEJ, July 2015.

  104. T. Matsubara, T. Sekine, and Y. Takahashi, "A simultaneous approximation method of attenuation and group delay characteristics for coupled resonators filter with real transmission zeros," IEICE Technical Report, vol. 115, no. 115, MW2015-41, pp. 19-22, June 2015.

  105. T. Matsubara, T. Sekine, and Y. Takahashi, "Constrained vector fitting and its application to filter characteristics approximation," IEICE Technical Report, vol. 115, no. 87, CAS2015-10, pp. 53-58, June 2015.

  106. D. Saito, T. Sekine, and Y. Takahashi, "Consideration of formulation for state equations of circuits based on the modi ed nodal analysis," 2015 Proceedings IEICE General Conference, vol. 2015, p. 1 (A-1-1), IEICE, March 2015.

  107. M. Sakai, T. Sekine, and Y. Takahashi, "Wirelessly powered circuit for low-power adiabatic logic circuits," 2015 Proceedings IEICE General Conference, vol. 2015, p. 2 (A-1-2), IEICE, March 2015.

  108. M. Sakai, T. Sekine, and Y. Takahashi, "Matching of wirelessly powered circuit for low-power adiabatic logic circuits," 2015 Proceedings IEICE General Conference, vol. 2015, p. 612 (B-21-11), IEICE, March 2015.

  109. M. Sakai, T. Sekine, and Y. Takahashi, "Investigation of wirelessly powered circuit for low-power adiabatic logic circuits," IEICE Technical Report, vol. 114, no. 498, MW2014-211, pp. 49-54, March 2015.

  110. D. Saito, T. Sekine, and Y. Takahashi, "A formulation of the state equations of the circuit based on the modified nodal analysis," IEICE Technical Report, vol. 114, no. 425, CAS2014-119, pp. 71-76, Jan. 2015.

  111. C. Monteiro, Y. Takahashi, T. Sekine, "Security evaluation of CSSAL countermeasure against side-channel attacks using frequency spectrum analysis," IEICE Technical Report, vol. 114, no. 381, EMCJ2014-82, pp. 75-80, Dec. 2014.

  112. S. Ouno, T. Sekine, and Y. Takahashi, "Investigation of S-parameters estimation method for two-port which is connected to fixture having unnecessary couplings," IEICE Technical Report, vol. 114, no. 267, MW2014-104, pp. 35-40, Oct. 2014.

  113. K. Kato, Y. Takahashi, and T. Sekine, "Post-layout simulation of 4×4-bit multiplier using subthreshold adiabatic logic circuit," 2014 Proceedings IEICE Society Conference, vol. 2014, p. 18 (A-1-18), IEICE, Sept. 2014.

  114. T. Matsubara, T. Sekine, and Y. Takahashi, "A synthesis method for coupled resonators filter with transmission zeros in any complex and real frequency using positive function and related equivalent transformations," IEICE Technical Report, vol. 114, no. 111, MW2014-45, pp. 17-22, June 2014.

  115. S. Ouno, T. Sekine, and Y. Takahashi, "Conditions of loads for 4-port S-parameter estimation by two or one-port measurements," IEICE Technical Report, vol. 114, no. 15, EMCJ2014-4, pp. 19-24, April 2014.

  116. C. Monteiro, Y. Takahashi, and T. Sekine, "Measurement of CSSAL Multiplier over GF(24) LSI Implemented in 0.18 µm CMOS Technology," 2014 Proceedings IEICE General Conference, vol. 2014, p. 2 (A-1-2), IEICE, March 2014.

  117. K. Kato, Y. Takahashi, and T. Sekine, "Comparison of energy consumption of subthreshold adiabatic logic circuit," 2014 Proceedings IEICE General Conference, vol. 2014, p. 3 (A-1-3), IEICE, March 2014.

  118. H. Ogata, Y. Takahashi, and T. Sekine, "Relationship between voltage waveforms and power dissipation for determination of memristance value," 2014 Proceedings IEICE General Conference, vol. 2014, p. 5 (A-1-5), IEICE, March 2014.

  119. S. Ohno, T. Sekine, and Y. Takahashi, "A estimation method of 4-port S-parameter," 2014 Proceedings IEICE General Conference, vol. 2014, p. 93 (C-2-63), IEICE, March 2014.

  120. T. Matsubara, T. Sekine, and Y. Takahashi, "Characteristic approximatation of filter functions by vector fitting," 2014 Proceedings IEICE General Conference, vol. 2014, p. 102 (C-2-72), IEICE, March 2014.

  121. L. Zhao, T. Sekine, and Y. Takahashi, "Comparison of energy consumption of the one or two phase adiabatic CMOS logic circuits," IEICE Technical Report, vol. 113, no. 427, CAS2013-83, pp. 53-57, Feb. 2014.

  122. S. Ouno, T. Sekine, and Y. Takahashi, "A method of 4-port S-parameter estimation by the two-port measurements," IEICE Technical Report, vol. 113, no. 427, CAS2013-86, pp. 67-70, Feb. 2014.

  123. N. Maeda, S. Fukui, T. Naoi, H. Ichikawa, T. Sekine, and Y. Takahashi, "Estimation for 2r-port S-parameters by the r-port measurements," IEICE Technical Report, vol. 113, no. 368, EMCJ2013-107, pp. 55-60, Dec. 2013.

  124. K. Ishida, T. Sekine, and Y. Takahashi, "An analysis of non uniform transmission line using CIP method," IEICE Technical Report, vol. 113, no. 368, EMCJ2013-108, pp. 61-66, Dec. 2013.

  125. R. Date, T. Sekine, and Y. Takahashi, "Estimation of the noise location on the transmission line by measuring the currents at the both ends," IEICE Technical Report, vol. 113, no. 368, EMCJ2013-110, pp. 73-78, Dec. 2013.

  126. [Invited Talk] Y. Takahashi, C. Monteiro, and T. Sekine, "CSSAL: Charge sharing symmetric adiabatic logic -Case study of logic circuit design and cryptographic circuit design-," IEICE Technical Report, vol. 113, no. 224, CAS2013-49, pp. 71-75, Sept. 2013.

  127. K. Kato, Y. Takahashi, and T. Sekine, "Operation verification of adiabatic logic in subthreshold region," IEICE Technical Report, vol. 113, no. 224, CAS2013-50, pp. 77-82, Sept. 2013.

  128. H. Ogata, Y. Takahashi, and T. Sekine, "Evaluation of synaptic weighting circuit with pulse-based memristor using adibatic driving," IEICE Technical Report, vol. 113, no. 224, CAS2013-51, pp. 83-87, Sept. 2013.

  129. C. Monteiro, Y. Takahashi, and T. Sekine, "LSI implementation of a secure low-power CSSAL cellular multiplier," IEICE Technical Report, vol. 113, no. 224, CAS2013-52, pp. 89-94, Sept. 2013.

  130. L. Zhao, T. Sekine, and Y. Takahashi, "Quasi adiabatic CMOS logic circuit using sinusoidal power clock," 2013 Tokai-Section Joint Convention of Institutes of Electrical and Information Engineers, G2-3, Sept. 2013.

  131. R. Date, T. Sekine, and Y. Takahashi, "Estimation of the noise location on the transmission line by measuring the currents at the both ends," 2013 Proceedings IEICE Society Conference, vol. 2013, p. 11 (A-1-11), IEICE, Sept. 2013.

  132. L. Zhao, T. Sekine, and Y. Takahashi, "Comparison of energy consumption of quasi adiabatic CMOS logic circuits," 2013 Proceedings IEICE Society Conference, vol. 2013, p. 12 (A-1-12), IEICE, Sept. 2013.

  133. H. Ogata, Y. Takahashi, and T. Sekine, "Evaluation of synaptic weighting circuit with pulse-based memristor using adibatic driving," 2013 Proceedings IEICE Society Conference, vol. 2013, p. 13 (A-1-13), IEICE, Sept. 2013.

  134. K. Kato, Y. Takahashi, and T. Sekine, "Operation verification of adiabatic logic in subthreshold region," 2013 Proceedings IEICE Society Conference, vol. 2013, p. 14 (A-1-14), IEICE, Sept. 2013.

  135. C. Monteiro, Y. Takahashi, and T. Sekine, "LSI implementation of a bit-Parallel cellular multiplier over GF(24) using charge-sharing symmetric adiabatic logic," 2013 Proceedings IEICE Society Conference, vol. 2013, p. 101 (C-12-41), IEICE, Sept. 2013.

  136. R. Date, T. Sekine, and Y. Takahashi, "Estimation of the position that the external electromagnetic field affect the transmission line by measuring the current at the end of transmission line," IEICE Technical Report, vol. 113, no. 125, EMCJ2013-44, pp. 29-32, July 2013.

  137. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "An estimation method for the 3 port S parameters of reciprocal circuits with 1 Port measurements," IEICE Technical Report, vol. 113, no. 101, EMCJ2013-20, pp. 45-49, June 2013.

  138. C. Monteiro, Y. Takahashi, and T. Sekine, "Low power CSSAL bit-parallel multiplier over GF(24) in 0.18 µm CMOS technology," IEICE Technical Report, vol. 113, no. 2, EMCJ2013-3, pp. 13-18, April 2013.

  139. L. Zhao, T. Sekine, and Y. Takahashi, "Investigation of the switching operation of the quasi adiabatic CMOS logic circuit," 2013 Proceedings IEICE General Conference, vol. 2013, p. 9 (A-1-9), IEICE, March 2013.

  140. N. Maeda, S. Fukui, T. Sekine, and Y. Takahashi, "Estimation of the n port S parameters with n-1 port measurements," 2013 Proceedings IEICE General Conference, vol. 2013, p. 393 (B-4-48), IEICE, March 2013.

  141. R. Date, T. Sekine, and Y. Takahashi, "A method for determining the voltage distribution on the transmission line by measuring the voltage at the end of the transmission line," IEICE Technical Report, vol. 112, no. 418, CAS2012-69, pp. 19-21, Jan. 2013.

  142. N. Maeda, S. Fukui, K. Ichikawa, Y. Sakurai, T. Sekine, and Y. Takahashi, "Estimation of the 3-port S parameters with 2-port measurements and its application to the immunity testing," IEICE Technical Report, vol. 112, no. 361, EMCJ2012-98, pp. 81-85, Dec. 2012.

  143. C. Monteiro, Y. Takahashi, and T. Sekine, "Survey on secure adiabatic logic for countermeasure against side-channel attacks," IEICE Technical Report, vol. 112, no. 361, EMCJ2012-100, pp. 95-100, Dec. 2012.

  144. L. Zhao, T. Sekine, and Y. Takahashi, "Frequency characteristics of CMOS Logic circuits using quasi adiabatic switching principle," 2012 Tokai-Section Joint Convention of Institutes of Electrical and Information Engineers, A1-8, Sept. 2012.

  145. K. Ishida, T. Sekine, and Y. Takahashi, "Discretization error of the ADI-FDTD method for transient analysis of lossy transmission line," 2012 Tokai-Section Joint Convention of Institutes of Electrical and Information Engineers, N4-6, Sept. 2012.

  146. Y. Urata, Y. Takahashi, and T. Sekine, "Power consumption evaluation of adiabatic 256-bit content addressable memory," 2012 Proceedings IEICE Society Conference, vol. 2012, p. 13 (A-1-13), IEICE, Sept. 2012.

  147. L. Zhao, T. Sekine, and Y. Takahashi, "CMOS logic circuits using quasi adiabatic switching principle," 2012 Proceedings IEICE Society Conference, vol. 2012, p. 14 (A-1-14), IEICE, Sept. 2012.

  148. Z. Luo, Y. Takahashi, and T. Sekine "DPFAL: Diode-based positive feedback diabatic logic," 2012 Proceedings IEICE Society Conference, vol. 2012, p. 16 (A-1-16), IEICE, Sept. 2012.

  149. K. Ishida, T. Sekine, and Y. Takahashi, "Discretization error of extended method of characteristics for transient analysis of lossy transmission line," 2012 Proceedings IEICE Society Conference, vol. 2012, p. 23 (A-1-23), IEICE, Sept. 2012.

  150. C. Monteiro, Y. Takahashi, and T. Sekine, "Investigation study of inner-cell bit-parallel multiplier over GF(2m) using secure adiabatic logic style," 2012 Proceedings IEICE Society Conference, vol. 2012, p. 116 (A-7-6), IEICE, Sept. 2012.

  151. Y. Takahashi, T. Sekine, and M. Yokoyama, "Performance analysis and power saving effect for subthreshold adiabatic logic," 2012 Proceedings IEICE Society Conference, vol. 2012, pp. S-13 - S-14 (AS-1-7), IEICE, Sept. 2012.

  152. I. Kumazaki, T. Sekine, and Y. Takahashi, "An improvement of time domain analysis using discrete Hilbert transform," 2012 Proceedings IEICE Society Conference, vol. 2012, p. 268 (C-15-14), IEICE, Sept. 2012.

  153. K. Murasawa, T. Sekine, and Y. Takahashi, "Comparison of methods of improving group delay characteristic for coupled resonators filter using complex transmission zeros," 2012 Proceedings IEICE Society Conference, vol. 2012, pp. S-25 - S-26 (CS-2-4), IEICE, Sept. 2012.

  154. Y. Nakajima, T. Sekine, and Y. Takahashi, "An consideration of Q-factor for sinusoidal oscillators," 2012 Proceedings IEICE Society Conference, vol. 2012, pp. S-37 - S-38 (CS-3-1), IEICE, Sept. 2012.

  155. T. Sekine, and Y. Takahashi, "Consideration of coupled lossy transmission line in an inhomogeneous medium using the time-domain mode decomposition," IEICE Technical Report, vol. 112, no. 109, MW2012-24, pp. 31-35, June 2012.

  156. K. Murasawa, T. Sekine, and Y. Takahashi, "An improvement of group delay characteristic for coupled resonators filter using complex transmission zeros," IEICE Technical Report, vol. 112, no. 109, MW2012-23, pp. 25-30, June 2012.

  157. C. Monteiro, Y. Takahashi, and T. Sekine, "A comparison of cellular multiplier cell for finite field GF(2m) using secure adiabatic logics," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-12, no. 3, pp. 73-77 (ECT-12-052), IEEJ, June 2012.

  158. K. Murasawa, T. Sekine, and Y. Takahashi "Improvement of group delay for asymmetric coupled low-pass prototype filters using all-pass function," 2012 Proceedings IEICE General Conference, vol. 2012, p. 40 (A-1-40), IEICE, March 2012.

  159. Y. Nakajima, T. Sekine, and Y. Takahashi, "Relation of phase noise and Q factor of sinusoidal oscillator," IEICE Technical Report, vol. 111, no. 377, CAS2011-97, pp. 67-70, Jan. 2012.

  160. Y. Kawasaki, T. Sekine, and Y. Takahashi, "Analysis of metamaterial transmission line with coupling between dielectric and magnetic flux density," IEICE Technical Report, vol. 111, no. 377, CAS2011-89, pp. 25-30, Jan. 2012.

  161. Y. Takahashi, and H. Sato, "A low power bias voltage generator for adiabatic logic," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-12, no. 1, pp. 19-24 (ECT-12-004), IEEJ, Jan. 2012.

  162. I. Kumazaki, T. Sekine, and Y. Takahashi, "A time domain analysis for nonuniform transmission line discrete using Hilbert transform," IEICE Technical Report, vol. 111, no. 242, CAS2011-42, pp. 55-60, Oct. 2011.

  163. H. Komiyama, Y. Takahashi, and T. Sekine "Adiabatic SRAM and its evaluation," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 19 (A-1-19), IEICE, Sept. 2011.

  164. C. Monteiro, Y. Takahashi, and T. Sekine "Evaluation of secure adiabatic dynamic and adiabatic differential logic for cryptographoc system," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 20 (A-1-20), IEICE, Sept. 2011.

  165. T. Kutsuna, Y. Takahashi, and T. Sekine "A study of low power phase locked loop circuit for adiabatic power supply," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 21 (A-1-21), IEICE, Sept. 2011.

  166. Z. Luo, Y. Takahashi, and T. Sekine "4N2P2D: Adiabatic logic circuit," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 22 (A-1-22), IEICE, Sept. 2011.

  167. Y. Urata, Y. Takahashi, and T. Sekine "Evaluation of memristor CAM with adiabatic driving," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 23 (A-1-23), IEICE, Sept. 2011.

  168. I. Kumazaki, T. Sekine, and Y. Takahashi, "A time domain analysis for transmission line discrete using Hilbert transform," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 30 (A-1-30), IEICE, Sept. 2011.

  169. Y. Kawasaki, T. Sekine, and Y. Takahashi, "A cascade matrix metamaterial transmission line with extended constitutive relationships," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 31 (A-1-31), IEICE, Sept. 2011.

  170. Y. Nakajima, T. Sekine, and Y. Takahashi, "Fundamental investigation of oscillator's Q," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 25 (C-2-1), IEICE, Sept. 2011.

  171. K. Murasawa, T. Sekine, and Y. Takahashi, "An improvement of group delay characteristic for coupled low-pass prototype filters using complex transmission zeros," 2011 Proceedings IEICE Society Conference, vol. 2011, p. 67 (C-2-43), IEICE, Sept. 2011.

  172. T. Sekine, and Y. Takahashi, "An analisis of convergence for extended method of characteristics," IEICE Technical Report, vol. 111, no. 205, EMCJ2011-80, pp. 49-53, Sept. 2011.

  173. Y. Kawasaki, T. Sekine, and Y. Takahashi, "Equivalent representation of metamaterial transmission line with coupling between dielectric and magnetic flux density," Proceedings IEICE the 24th Workshop on Circuits and Systems, pp. 289-293, Aug. 2011 (Refereed).

  174. K. Murasawa, T. Sekine, and Y. Takahashi, "A method of maximaly flat attenuation and equal ripple group delay characteristic approximation for coupling resonators filter," IEICE Technical Report, vol. 111, no. 95, MW2011-35, pp. 17-22, June 2011.

  175. Y. Takahashi, Y. Urata, T. Sekine, and M. Yokoyama, "Evaluation of memristor-based 1T-SRAM with adiabatic driving," 2011 Proceedings IEICE General Conference, vol. 2011, p. 10 (A-1-10), IEICE, March 2011.

  176. Y. Kawasaki, T. Sekine, and Y. Takahashi, "Equivalent representation of metamaterial transmission line consist of extended constitutive relationships," 2011 Proceedings IEICE General Conference, vol. 2011, p. 20 (A-1-20), IEICE, March 2011.

  177. Y. Kawasaki, T. Sekine, and Y. Takahashi, "Consideration of metamaterial transmission line with extended constitutive relationships by using circuit theory," IEICE Technical Report, vol. 110, no. 447, MW2010-152, pp. 1-6, March 2011.

  178. A. Inoue, T. Sekine, and Y. Takahashi, "Equivalent transformation of coupled filter consist of parallel connected lowpass sections by using similarity transformation of coupling matrix," IEICE Technical Report, vol. 110, no. 237, MW2010-87, pp. 1-6, Oct. 2010.

  179. A. Inoue, T. Sekine, and Y. Takahashi, "External quality factor and coupling coefficient for filters using different resonance coupling resonators," 2010 Proceedings IEICE Society Conference, vol. 2010, p. 25 (A-1-25), IEICE, Sept. 2010.

  180. K. Oda, T. Sekine, and Y. Takahashi, "A convergence of extended method of characteristics for transmission line analysis," 2010 Proceedings IEICE Society Conference, vol. 2010, p. 27 (A-1-27), IEICE, Sept. 2010.

  181. K. Oda, T. Sekine, and Y. Takahashi, "Stability and convergence analysis of extended method of characteristics for transmission line ," IEICE Technical Report, vol. 110, no. 194, EMCJ2010-50, pp. 53-58, Sept. 2010.

  182. Y. Kawasaki, T. Sekine, and Y. Takahashi, "Application of fast inverse laplace transform to transmission line analysis," IEICE Technical Report, vol. 110, no. 18, EMCJ2010-5, pp. 25-30, April 2010.

  183. A. Inoue, T. Sekine, and Y. Takahashi, "A synthesis of low order coupled filter with attenuation poles at frequency domain," 2010 Proceedings IEICE General Conference, vol. 2010, p. 15 (A-1-15), IEICE, March 2010.

  184. K. Oda, T. Sekine, and Y. Takahashi, "Transient analysis of linear tapered transmission line using extended method of characteristics," 2010 Proceedings IEICE General Conference, vol. 2010, p. 16 (A-1-16), IEICE, March 2010.

  185. Y. Takahashi, T. Asai, T. Sekine, and M. Yokoyama, "Evaluation for power analysis attack of adiabatic logic," 2010 Proceedings IEICE General Conference, p. 17 (A-1-17), IEICE, March 2010.

  186. N. A. Nayan, Y. Takahashi, and T. Sekine, "Overlapped-voltage clock driver and low peak voltage evaluation for 2PASCL," 2010 Proceedings IEICE General Conference, vol. 2010, p. 18 (A-1-18), IEICE, March 2010.

  187. A. Inoue, T. Sekine, and Y. Takahashi, "A general synthesis method of coupled filter with transmission zeros consist of parallel connected lowpass sectons," IEICE Technical Report, vol. 109, no. 431, MW2009-184, pp. 31-36, March 2010.

  188. A. Inoue, T. Sekine, and Y. Takahashi, "A synthesis method of coupled filter with transmission zeros consist of parallel connected lowpass sectons," IEICE Technical Report, vol. 109, no. 242, MW2009-115, pp. 129-134, Oct. 2009.

  189. K. Oda, T. Sekine, and Y. Takahashi, "Transmission line analysis using extended method of characteristics," IEICE Technical Report, vol. 109, no. 242, MW2009-116, pp. 135-140, Oct. 2009.

  190. Y. Tomita, Y. Takahashi, and T. Sekine, "The proposed PTL circuit using the adiabatic logic and power consumption comparion with the conventional logic," 2009 Proceedings IEICE Society Conference, vol. 2009, p. 3 (A-1-3), IEICE, Sept. 2009.

  191. K. Oda, T. Sekine, and Y. Takahashi, "Transmission line analysis using extended method of characteristics that can specify arbitrary space and time interval," 2009 Proceedings IEICE Society Conference, vol. 2009, p. 4 (A-1-4), IEICE, Sept. 2009.

  192. A. Inoue, T. Sekine, and Y. Takahashi, "A Synthesis method of coupled filter consist of parallel connected lowpass sections," 2009 Proceedings IEICE Society Conference, vol. 2009, p. 5 (A-1-5), IEICE, Sept. 2009.

  193. S. Takeuchi, Y. Takahashi, and T. Sekine, "A distortion ratio of op-amp used for a class-D amplifier," 2009 Proceedings IEICE General Conference, vol. 2009, p. 43 (A-1-43), IEICE, March 2009.

  194. K. Kato, Y. Takahashi, and T. Sekine, "A frequency of common subexpression in multiplierless FIR filter," 2009 Proceedings IEICE General Conference, vol. 2009, p. 44 (A-1-44), IEICE, March 2009.

  195. T. Hirose, T. Sekine, and Y. Takahashi, "Evaluation of approximate expression of skin effect in time domain," 2009 Proceedings IEICE General Conference, vol. 2009, p. 45 (A-1-45), IEICE, March 2009.

  196. S. Fukatsu, T. Sekine, and Y. Takahashi, "Stability analysis of difference methods for lossy transmission line," 2009 Proceedings IEICE General Conference, vol. 2009, p. 46 (A-1-46), IEICE, March 2009.

  197. N. A. Nayan, Y. Takahashi, and T. Sekine, "Two phase clocked adiabatic static logic circuit: A proposal for digital low power applications," 2009 Proceedings IEICE General Conference, vol. 2009, p. 102 (C-12-14), IEICE, March 2009.

  198. S. Nagano, Y. Takahashi, T. Sekine, and M. Yokoyama, "On-chip sinusoidal wave power supply circuit for adiabatic logic," 2009 Proceedings IEICE General Conference, vol. 2009, p. 105 (C-12-17), IEICE, March 2009.

  199. S. Fukatsu, T. Sekine, and Y. Takahashi, "Comparison between Yee's FDTD method and center difference method by using stability analysis," IEICE Technical Report, vol. 108, no. 477, NLP2008-154, pp. 19-24, March 2009.

  200. K. Watanabe, T. Sekine, Y. Takahashi, and K. Kobayashi, "Analysis of nonuniform transmission line in the frequency domain using wavelet expansion," IEICE Technical Report, vol. 108, no. 367, EMCJ2008-87, pp. 7-12, Dec. 2008.

  201. N. A. Nayan, Y. Takahashi, and T. Sekine, "Low-power adiabatic logic circuit: Simulation and energy dissipation comparison," IEICE Technical Report, vol. 108, no. 347, ICD2008-126, pp. 125-130, Dec. 2008.

  202. T. Sekine, T. Hirose, Y. Takahashi, and K. Kobayashi, "Relation between transmission line loss and its time-domain responses," IEICE Technical Report, vol. 108, no. 256, EMCJ2008-63, pp. 23-28, Oct. 2008.

  203. T. Sekine, Y. Takahashi, K. Kobayashi, "Relation between transmission line loss and eye diagram," 2008 Proceedings IEICE General Conference, vol. 2008, p. 1 (A-1-1), IEICE, March 2008.

  204. T. Ikeda, T. Sekine, Y. Takahashi, and K. Kobayashi, "A design of low pass filter with attenuation poles using parallel connected commensurate transmission line low pass sections," IEICE Technical Report, vol. 107, no. 475, CAS2007-90, pp. 37-42, Jan. 2008.

  205. N. Ichimura, T. Sekine, Y. Takahashi, and K. Kobayashi, "A wide band design of double-sided and transparent wave absorber with specified reflection and transmission coefficients," IEICE Technical Report, vol. 107, no. 371, EMCJ2007-104, pp. 49-53, Dec. 2007.

  206. Y. Takahashi, T. Sekine, and M. Yokoyama, "A 4×4-bit multiplier in a two phase drive adiabatic dynamic CMOS logic," 2007 System LSI Workshop, IEICE, pp. 320-322, Nov. 2007. (PDF File: 342kB, Poster, in Japanese, MD5: 737f7d9d47f368197a41b777faa82e73)

  207. Y. Sakai, Y. Fukuta, Y. Takahashi, T. Sekine, and M. Yokoyama, "Two-phase clocked-CMOS adiabatic dynamic logic," 2007 System LSI Workshop, IEICE, pp. 249-251, Nov. 2007. (PDF File: 194kB, Poster, in Japansese, MD5: 9392efcd5b698256ed84842e93801396)

  208. Y. Fukuta, Y. Sakai, Y. Takahashi, T. Sekine, and M. Yokoyama, "Analysis of power supply circuit using a two-phase clocked-CMOS adiabatic dynamic logic," 2007 System LSI Workshop, IEICE, pp. 252-254, Nov. 2007. (PDF File: 169kB, Poster, in Japanese, MD5: 611cd9c01391de134db10a7503b94147)

  209. K. Watanabe, T. Sekine, Y. Takahashi, and K. Kobayashi, "Analysis of nonuniform transmission line equations using Yee-lattice and wavelet expansion," 2007 Proceedings IEICE Society Conference, vol. 2007, p. 14 (A-1-14), IEICE, Sept. 2007.

  210. Y. Takahashi, D. Tsuzuki, T. Sekine, and M. Yokoyama, "Design of 16-bit RISC CPU using two phase drive adiabatic dynamic CMOS logic," 2007 Proceedings IEICE General Conference, vol. 2007, p. 10 (A-1-10), IEICE, March 2007.

  211. T. Ikeda, T. Sekine, Y. Takahashi, and K. Kobayashi, "A design of low pass filter with attenuation poles using parallel connected commensurate transmission lines," 2007 Proceedings IEICE General Conference, vol. 2007, p. 13 (A-1-13), IEICE, March 2007.

  212. N. Ichimura, T. Sekine, Y. Takahashi, and K. Kobayashi, "Two-layered permeable wave absorber," 2007 Proceedings IEICE General Conference, vol. 2007, p. 18 (A-1-18), IEICE, March 2007.

  213. D. Ichikawa, T. Sekine, Y. Takahashi, and K. Kobayashi, "A improvement of the incorporation of terminal constraints for the inverse-FDTD method," 2007 Proceedings IEICE General Conference, vol. 2007, p. 35 (A-1-35), IEICE, March 2007.

  214. T. Sekine, Y. Takahashi and K. Kobayashi, "Transmission line analysis using Yee FDTD method," 2006 Proceedings IEICE Society Conference, vol. 2006, p. 1 (A-1-19), IEICE, Sept. 2006.

  215. A. Adachi, T. Sekine, Y. Takahashi and K. Kobayashi, "Convergence of nonuniform transmission line synthesis using Kalman filter," 2006 Tokai-Section Joint Convention of Institutes of Electrical and Information Engineers, C-246, Sept. 2006.

  216. D. Ichikawa, T. Sekine, Y. Takahashi and K. Kobayashi, "Representation of equivalent circuit for bending lossy micro strip structure," 2006 Tokai-Section Joint Convention of Institutes of Electrical and Information Engineers, C-247, Sept. 2006.

  217. Y. Horibe, T. Sekine, Y. Takahashi and K. Kobayashi, "Numerical dispersion of lossy transmission line analysis using the extended method of characteristics," 2006 Tokai-Section Joint Convention of Institutes of Electrical and Information Engineers, C-248, Sept. 2006.

  218. D. Ichikawa, T. Sekine, Y. Takahashi and K. Kobayashi, "A synthsis method of nonuniform transmission line by S parameter measurements," IEICE Technical Report, vol. 106, no. 34, MW2006-34, pp. 53-58, June 2006.

  219. T. Sekine, Y. Takahashi, and K. Kobayashi, "A extended method of characteristics in transmission line analysis and its numerical stability," 2006 Proceedings IEICE General Conference, vol. 2006, p. 13 (A-1-13), IEICE, March 2006.

  220. Y. Horibe, Y. Takahashi, T. Sekine, and K. Kobayashi, "A extended method of characteristics in transmission line analysis and its numerical stability," IEICE Technical Report, vol. 105, no. 454, EMCJ2005-120, pp. 35-40, Dec. 2005.

  221. A. Adachi, Y. Takahashi, T. Sekine, and K. Kobayashi, "Synthesis of lossy nonuniform Transmission Line that uses measured data with noise," 2005 Proceedings IEICE Society Conference, vol. 2005, p. 1 (A-1-1), IEICE, Sept. 2005.

  222. Y. Horibe, Y. Takahashi, T. Sekine, and K. Kobayashi, "Numerical dispersion of transmission line analysis using Crank-Nicolson scheme," 2005 Proceedings IEICE Society Conference, vol. 2005, p. 2 (A-1-2), IEICE, Sept. 2005.

  223. Y. Horibe, Y. Takahashi, T. Sekine, and K. Kobayashi, "Numerical stability of nonuniform transmission line analysis using Crank-Nicolson schme," IEICE Technical Report, vol. 105, no. 151, MW2005-38, pp. 33-38, June 2005.

  224. A. Adachi, Y. Takahashi, T. Sekine, and K. Kobayashi, "Time domain synthesis of nonuniform transmission line using Kalman filter," IEICE Technical Report, vol. 105, no. 151, MW2005-39, pp. 39-44, June 2005.

  225. Y. Takahashi, M. Yokoyama, K. Shouno, M. Mizunuma, and K. Takahashi, "A 4bit carry propagation free adder/subtracter VLSI using adiabatic dynamic CMOS logic circuit technology," 2002 Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, 1C-02, Aug. 2002. (PDF File: 23kB, in Japanese, MD5: b02a36668e81559a9941fe8565ad0994)

  226. K. Kohara, Y. Takahashi, K. Takahashi, M. Yokoyama, and K. Shouno, "IIR Hilbert transformer using poly-phase switched capacitor technology" 2002 Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, 1C-03, Aug. 2002.

  227. Y. Takahashi, T. Kitajima, and K. Takahashi, "Hilbert transformer design using CSD FIR filter," The Papers of Technical Meeting on Electronic circuits, IEE Japan, vol. ECT-01, no. 43, pp. 7-12 (ECT-01-043), IEEJ, June 2001. (PDF File: 86kB, in Japanese, MD5: 8c71f8203987bcf5abb34af2126f081e)

  228. Y. Takahashi, K. Takahashi, "Hilbert Transformer design using CSD FIR filter," 2001 Proceedings IEICE General Conference, vol. 2001, no. Electronics 2, p. 98 (C-12-3), IEICE, March 2001.





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