Hinata Tajima, Yuya Hatanaka, Daisuke Ito, Yasuhiro
Takahashi, Makoto Nakamura, Toshiyuki Inoue, Keiji
Kishine, ``High-Speed NRZ–DPSK Conversion Circuit
Using CMOS Logic Gates with Half-Rate Architecture,''
Proc. of The 25th International Conference on
Electronics, Information, and Communication (ICEIC), pp.
659--663, 2026. 2026年度
IEEE名古屋支部国際会議研究発表賞
Tsubasa Yabutani, Makoto Nakamura, and Daisuke Ito, ``PAM4 driver circuit with two stacked stages in 0.18-µm CMOS for electro-absorption modulators,'' 2025 International Symposium on Nonlinear Theory and Its Applications (NOLTA2025), pp. 128--131, 2025.
大鹿純聖, 石田翔悟, 伊藤大輔, 中村誠, ``高速PAM4信号対応線形性補償VCSELドライバ回路の検討,'' 電子情報通信学会論文誌 A, vol. J108-A, no. 5, pp. 112-115, 2025. [link]
石田翔悟, 大鹿純聖, 伊藤大輔, 中村誠, ``スタック型部分等化技術を用いたPAM4符号対応アナログ補償回路の検討,'' 電子情報通信学会論文誌 A, vol. J108-A, no. 7, pp., 2025 (in press).
Takuma Yamada, Daisuke Ito, and Makoto Nakamura, ``Gain Enhancement Technique for a Wideband Transimpedance Amplifier with Common Gate Feedforward in Optical Communication,'' IEICE Electronics Express (ELEX), vol. 22, No. 1, pp. 20240597, 2025.